SN65MLVD201
- Low-Voltage Differential 30-
Line Drivers and Receivers for Signaling Rates(1) Up to 200 Mbps - Type-1 Receivers Incorporate 25 mV of Hysteresis
- Type-2 Receivers Provide an Offset (100 mV) Threshold to Detect Open-Circuit and Idle-Bus Conditions
- Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange
- Controlled Driver Output Voltage Transition Times for Improved Signal Quality
- –1 V to 3.4 V Common-Mode Voltage Range Allows Data Transfer With 2 V of Ground Noise
- Bus Pins High Impedance When Disabled or VCC ≤ 1.5 V
- 100-Mbps Devices Available (SN65MLVD200A, 202A, 204A, 205A)
- M-LVDS Bus Power Up/Down Glitch Free
- APPLICATIONS
- Low-Power High-Speed Short-Reach
Alternative to TIA/EIA-485 - Backplane or Cabled Multipoint Data and Clock Transmission
- Cellular Base Stations
- Central-Office Switches
- Network Switches and Routers
- Low-Power High-Speed Short-Reach
(1) The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
The SN65MLVD201, 203, 206, and 207 are multipoint-low-voltage differential (M-LVDS) line drivers and receivers, which are optimized to operate at signaling rates up to 200 Mbps. All parts comply with the multipoint low-voltage differential signaling (M-LVDS) standard TIA/EIA-899. These circuits are similar to their TIA/EIA-644 standard compliant LVDS counterparts, with added features to address multipoint applications. The driver output has been designed to support multipoint buses presenting loads as low as 30 , and incorporates controlled transition times to allow for stubs off of the backbone transmission line.
These devices have Type-1 and Type-2 receivers that detect the bus state with as little as 50 mV of differential input voltage over a common-mode voltage range of –1 V to 3.4 V. The Type-1 receivers exhibit 25 mV of differential input voltage hysteresis to prevent output oscillations with slowly changing signals or loss of input. Type-2 receivers include an offset threshold to provide a known output state under open-circuit, idle-bus, and other faults conditions. The devices are characterized for operation from –40°C to 85°C.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | Multipoint-LVDS Line Driver and Receiver datasheet (Rev. C) | 2008年 1月 7日 | |
| Application brief | How Far, How Fast Can You Operate MLVDS? | 2018年 8月 6日 | ||
| Application note | Introduction to M-LVDS (TIA/EIA-899) (Rev. A) | 2013年 1月 3日 | ||
| User guide | Multipoint-Low Voltage Differential Signaling (M-LVDS) EVM (Rev. B) | 2004年 4月 5日 | ||
| Application note | M-LVDS Signaling Rate Versus Distance | 2003年 4月 9日 | ||
| Application note | Interoperability of M-LVDS and BusLVDS | 2003年 2月 6日 | ||
| User guide | 200 Mbps Multipoint-Low Voltage Differential Signaling (M-LVDS) EVM (Rev. A) | 2002年 12月 20日 | ||
| Application note | Wired-Logic Signaling with M-LVDS | 2002年 10月 31日 | ||
| User guide | Multipoint-Low Voltage Differential Signaling (M-LVDS) Evaluation Module | 2002年 3月 4日 | ||
| Application note | TIA/EIA-485 and M-LVDS, Power and Speed Comparison | 2002年 2月 20日 |
設計與開發
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MLVD20XEVM — M-LVDS 評估模組
The SN65MLVD203B is a full-duplex transceiver, and the SN65MLVD204B is a half-duplex transceiver.
SN65MLVD2-3EVM — SN65MLVD2-3EVM 評估模組
The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to250 Mbps. Each receiver channel is controlled by a receive enable (/RE). When /RE = low, (...)
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。