SN74221
- Dual Versions of Highly Stable SN54121 and SN74121 One Shots
- SN54221 and SN74221 Demonstrate Electrical and Switching Characteristics That Are Virtually Identical to the SN54121 and SN74121 One Shots
- Pinout Is Identical to the SN54123, SN74123, SN54LS123, and SN74LS123
- Overriding Clear Terminates Output Pulse
The '221 and 'LS221 devices are monolithic dual multivibrators with performance characteristics virtually identical to those of the '121 devices. Each multivibrator features a negative-transition- triggered input and a positive-transition-triggered input, either of which can be used as an inhibit input.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with transition rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high immunity to VCC noise, typically of 1.5 V, is also provided by internal latching circuitry.
Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration relative to the output pulse. Output pulse length can be varied from 35 ns to the maximums shown in the above table by choosing appropriate timing components. With Rext = 2 k and Cext = 0, an output pulse typically of 30 ns is achieved, which can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics waveforms.
Pulse-width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability is limited only by the accuracy of external timing components.
Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing capacitance (10 pF to 10 µF) and more than one decade of timing resistance (2 k can be used. Also, the range of jitter-free output pulse widths is extended if VCC is held to 5 V and free-air temperature is 25°C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher duty cycles are available if a certain amount of pulse-width jitter is allowed.
The variance in output pulse width from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the '221 is shown in Figure 3. Variations in output pulse width versus supply voltage and temperature for the '221 are shown in Figures 4 and 5, respectively.
Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123 so that the '221 or 'LS221 devices can be substituted for those products in systems not using the retrigger by merely changing the value of Rext and/or Cext; however, the polarity of the capacitor must be changed.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | SN54221, SN54LS221, SN74221, SN74LS221 datasheet (Rev. B) | 2004年 11月 9日 | |
Application note | Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A) | PDF | HTML | 2020年 3月 13日 | |
Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
Application note | Designing With Logic (Rev. C) | 1997年 6月 1日 | ||
Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996年 10月 1日 | ||
Application note | Live Insertion | 1996年 10月 1日 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
PDIP (N) | 16 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點