SN74AUC1G125

Name: SN74AUC1G125
Brand: TI
SKU: SN74AUC1G125
Price: 0.202 USD

現行

具有 3 態輸出的單路 0.8-V 至 2.7-V 高速緩衝器

立即訂購

產品規格表

document-pdfAcrobat SN74AUC1G125 Single Bus Buffer Gate With 3-State Output datasheet (Rev. M) (英文) PDF | HTML

SN74AUC1G125

現行

產品規格表

立即訂購

產品詳細資料

Technology family

AUC

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

2.7

Number of channels

1

IOL (max) (mA)

9

Supply current (max) (µA)

10

IOH (max) (mA)

-9

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

AUC

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

2.7

Number of channels

1

IOL (max) (mA)

9

Supply current (max) (µA)

10

IOH (max) (mA)

-9

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

DSBGA (YZP)

5

2.1875 mm² 1.75 x 1.25

SOT-23 (DBV)

5

8.12 mm² 2.9 x 2.8

SOT-SC70 (DCK)

5

4.2 mm² 2 x 2.1

Optimized for 1.8-V operation
±8-mA output drive at 1.8 V
Maximum t_pd of 2.5 ns at 1.8 V, 30 pF load
Wide operating voltage range of 0.8 V to 2.7 V
Over-voltage tolerant I/Os support up to 3.6 V, independent of V_CC
Available in the Texas Instruments NanoFree™ package
I_off feature supports partial power down mode and back drive protection
Low power consumption, 10-µA maximum I_CC
Latch-up performance exceeds 100 mA per JESD 78, Class II

Optimized for 1.8-V operation
±8-mA output drive at 1.8 V
Maximum t_pd of 2.5 ns at 1.8 V, 30 pF load
Wide operating voltage range of 0.8 V to 2.7 V
Over-voltage tolerant I/Os support up to 3.6 V, independent of V_CC
Available in the Texas Instruments NanoFree™ package
I_off feature supports partial power down mode and back drive protection
Low power consumption, 10-µA maximum I_CC
Latch-up performance exceeds 100 mA per JESD 78, Class II

The SN74AUC1G125 device is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.

The AUC logic family is specifically designed for speed and is optimized for operation between 1.65-V and 1.95-V V_CC. With an optimal supply and 15-pF load the device can operate at over 250 MHz, or 500 Mbps. The unique output structure of the AUC family provides great signal integrity without the need for external termination when driving 50- to 65-Ω transmission lines of moderate length (less than 15 cm). See Application of the Texas Instruments AUC Sub-1-V Little Logic Devices for more details on this technology.

This device is available in the popular SOT-23 and SC70 packages, as well as the advanced NanoFree™ DSBGA package. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

The SN74AUC1G125 device is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.

The AUC logic family is specifically designed for speed and is optimized for operation between 1.65-V and 1.95-V V_CC. With an optimal supply and 15-pF load the device can operate at over 250 MHz, or 500 Mbps. The unique output structure of the AUC family provides great signal integrity without the need for external termination when driving 50- to 65-Ω transmission lines of moderate length (less than 15 cm). See Application of the Texas Instruments AUC Sub-1-V Little Logic Devices for more details on this technology.

This device is available in the popular SOT-23 and SC70 packages, as well as the advanced NanoFree™ DSBGA package. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

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SN74AUP1G125

現行

具有 3 態輸出的單路 0.8-V 至 3.6-V 低功耗緩衝器 Larger voltage range (0.8V to 3.6V), lower average drive strength (4mA)

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	類型	標題		日期
*	Data sheet	SN74AUC1G125 Single Bus Buffer Gate With 3-State Output datasheet (Rev. M)	PDF \| HTML	2022年 8月 15日
	Selection guide	Little Logic Guide 2018 (Rev. G)		2018年 7月 6日
	Selection guide	Logic Guide (Rev. AB)		2017年 6月 12日
	Application note	How to Select Little Logic (Rev. A)		2016年 7月 26日
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		2015年 12月 2日
	User guide	LOGIC Pocket Data Book (Rev. B)		2007年 1月 16日
	Product overview	Design Summary for WCSP Little Logic (Rev. B)		2004年 11月 4日
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004年 7月 8日
	Application note	Selecting the Right Level Translation Solution (Rev. A)		2004年 6月 22日
	User guide	Signal Switch Data Book (Rev. A)		2003年 11月 14日
	Application note	Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus Devices		2003年 3月 21日
	User guide	AUC Data Book, January 2003 (Rev. A)		2003年 1月 1日
	Application note	Texas Instruments Little Logic Application Report		2002年 11月 1日
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		2002年 8月 29日
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards		2002年 6月 13日
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS		2002年 3月 27日
	More literature	AUC Product Brochure (Rev. A)		2002年 3月 18日