SN74AVC1T45

Name: SN74AVC1T45
Brand: TI
SKU: SN74AVC1T45
Price: 0.141 USD

現行

具有可配置電平移位變化和 3 態輸出的單一位元雙電源供電匯流排收發器

立即訂購

產品規格表

document-pdfAcrobat SN74AVC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs datasheet (Rev. J) (英文) PDF | HTML

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SN74AXC1T45

現行

單位元雙電源匯流排收發器 Pin-to-pin upgrade with a wider voltage range and improved performance

SN74AVC1T45

現行

產品規格表

立即訂購

產品詳細資料

Technology family

AVC

Applications

GPIO

Bits (#)

1

High input voltage (min) (V)

0.78

High input voltage (max) (V)

3.6

Vout (min) (V)

1.2

Vout (max) (V)

3.6

Data rate (max) (Mbps)

500

IOH (max) (mA)

-12

IOL (max) (mA)

12

Supply current (max) (µA)

20

Features

Output enable, Overvoltage tolerant inputs, Partial power down (Ioff)

Input type

Standard CMOS

Output type

3-State, Balanced CMOS, Push-Pull

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

AVC

Applications

GPIO

Bits (#)

1

High input voltage (min) (V)

0.78

High input voltage (max) (V)

3.6

Vout (min) (V)

1.2

Vout (max) (V)

3.6

Data rate (max) (Mbps)

500

IOH (max) (mA)

-12

IOL (max) (mA)

12

Supply current (max) (µA)

20

Features

Output enable, Overvoltage tolerant inputs, Partial power down (Ioff)

Input type

Standard CMOS

Output type

3-State, Balanced CMOS, Push-Pull

Rating

Catalog

Operating temperature range (°C)

-40 to 85

DSBGA (YZP)

6

2.1875 mm² 1.75 x 1.25

SOT-23 (DBV)

6

8.12 mm² 2.9 x 2.8

SOT-5X3 (DRL)

6

2.56 mm² 1.6 x 1.6

SOT-SC70 (DCK)

6

4.2 mm² 2 x 2.1

Available in the Texas Instruments NanoFree™ package
Fully configurable dual-rail design allows each port to operate over the full 1.08V to 3.6V power-supply range
VCC isolation feature – if either VCC input is at GND, then both ports are in the high-impedance state
DIR input circuit referenced to VCCA
±12mA output drive at 3.3V
I/Os are 4.6V tolerant
Ioff supports partial-power-down mode operation
Typical maximum data rates
- 500Mbps (1.08V to 3.3V translation)
- 320Mbps (<1.8V to 3.3V translation)
- 320Mbps (translate to 2.5V or 1.8V)
- 280Mbps (translate to 1.5V)
- 240Mbps (translate to 1.2V)
Latch-up performance exceeds 100mA per JESD 78, Class II
ESD protection exceeds JESD 22
- ±2000V Human Body Model (A114-A)
- 200V Machine Model (A115-A)
- ±1000V Charged-Device Model (C101)

Available in the Texas Instruments NanoFree™ package
Fully configurable dual-rail design allows each port to operate over the full 1.08V to 3.6V power-supply range
VCC isolation feature – if either VCC input is at GND, then both ports are in the high-impedance state
DIR input circuit referenced to VCCA
±12mA output drive at 3.3V
I/Os are 4.6V tolerant
Ioff supports partial-power-down mode operation
Typical maximum data rates
- 500Mbps (1.08V to 3.3V translation)
- 320Mbps (<1.8V to 3.3V translation)
- 320Mbps (translate to 2.5V or 1.8V)
- 280Mbps (translate to 1.5V)
- 240Mbps (translate to 1.2V)
Latch-up performance exceeds 100mA per JESD 78, Class II
ESD protection exceeds JESD 22
- ±2000V Human Body Model (A114-A)
- 200V Machine Model (A115-A)
- ±1000V Charged-Device Model (C101)

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC1T45 is operational with VCCA/VCCB as low as 1.08V.

The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.08V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.08V to 3.6V. This allows for universal low-voltage, bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC1T45 is designed so that the DIR input is powered by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC1T45 is operational with VCCA/VCCB as low as 1.08V.

The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.08V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.08V to 3.6V. This allows for universal low-voltage, bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC1T45 is designed so that the DIR input is powered by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

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	類型	標題		日期
*	Data sheet	SN74AVC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs datasheet (Rev. J)	PDF \| HTML	2024年 8月 24日
	Application note	Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators	PDF \| HTML	2024年 10月 2日
	Application note	Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators	PDF \| HTML	2024年 7月 12日
	Application note	Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A)	PDF \| HTML	2024年 7月 3日
	EVM User's guide	Generic AVC and LVC Direction Controlled Translation EVM (Rev. B)		2021年 7月 30日
	Selection guide	Voltage Translation Buying Guide (Rev. A)		2021年 4月 15日
	Selection guide	Logic Guide (Rev. AB)		2017年 6月 12日
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		2015年 12月 2日
	Application note	Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B)		2015年 4月 30日
	Test report	TI Power Reference Design for Xilinx® Artix®-7 (AC701)		2014年 5月 12日
	User guide	PMP7977 User's Guide		2013年 9月 11日
	User guide	LOGIC Pocket Data Book (Rev. B)		2007年 1月 16日
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004年 7月 8日
	Application note	Selecting the Right Level Translation Solution (Rev. A)		2004年 6月 22日
	More literature	LCD Module Interface Application Clip		2003年 5月 9日
	User guide	AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C)		2002年 8月 20日
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards		2002年 6月 13日
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)		2002年 5月 22日
	Application note	Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B)		1999年 7月 7日
	Application note	AVC Logic Family Technology and Applications (Rev. A)		1998年 8月 26日

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