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緩衝器、驅動器和收發器
非反相緩衝器和驅動器

SN74HC244

現行

具有 3 態輸出的 8 通道 2-V 至 6-V 緩衝器

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產品規格表

SN74HC244

現行
產品規格表 立即訂購

產品詳細資料

Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 8 IOL (max) (mA) 7.8 Supply current (max) (µA) 80 IOH (max) (mA) -7.8 Input type Standard CMOS Output type 3-State Features Balanced outputs, Input clamp diode, Very high speed (tpd 5-10ns) Rating Automotive, Catalog Operating temperature range (°C) -40 to 85
Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 8 IOL (max) (mA) 7.8 Supply current (max) (µA) 80 IOH (max) (mA) -7.8 Input type Standard CMOS Output type 3-State Features Balanced outputs, Input clamp diode, Very high speed (tpd 5-10ns) Rating Automotive, Catalog Operating temperature range (°C) -40 to 85
PDIP (N) 20 228.702 mm² 24.33 x 9.4 SOIC (DW) 20 131.84 mm² 12.8 x 10.3 SOP (NS) 20 98.28 mm² 12.6 x 7.8 SSOP (DB) 20 56.16 mm² 7.2 x 7.8 TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Wide Operating Voltage Range of 2 V to 6 V
  • High-Current Outputs Drive Up to 15 LSTTL Loads
  • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
  • Low Power Consumption: ICC, 80-µA (Maximum)
  • Typical tpd = 11 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA (Maximum)
  • On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.
  • Wide Operating Voltage Range of 2 V to 6 V
  • High-Current Outputs Drive Up to 15 LSTTL Loads
  • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
  • Low Power Consumption: ICC, 80-µA (Maximum)
  • Typical tpd = 11 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA (Maximum)
  • On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.

The SNx4HC244 octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The SNx4HC244 devices are organized as two 4-bit buffers and drivers with separate output-enable (OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

The SNx4HC244 octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The SNx4HC244 devices are organized as two 4-bit buffers and drivers with separate output-enable (OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.
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類型 標題 日期
* Data sheet SNx4HC244 Octal Buffers and Line Drivers With 3-State Outputs datasheet (Rev. F) 2022年 5月 9日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Application note Optimizing AC Drive Control Panel Systems With Logic and Translation Use Cases 2021年 1月 20日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Simultaneous-Switching Performance of TI Logic Devices (Rev. B) 2005年 2月 23日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 1996年 5月 1日
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

設計與開發

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開發板

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14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

使用指南: PDF | HTML
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模擬型號

SN74HC244 Behavioral SPICE Model

SCLM219.ZIP (7 KB) - PSpice Model
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模擬型號

SN74HC244 IBIS Model (Rev. A)

SCHM004A.ZIP (25 KB) - IBIS Model
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
PDIP (N) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian
SOP (NS) 20 Ultra Librarian
SSOP (DB) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
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訂購與品質

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  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

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