SN74LV1T32
- Single-supply voltage translator at 5.0V, 3.3V, 2.5V, and 1.8V VCC
- Operating range of 1.8V to 5.5V
- Up translation:
- 1.2V(1) to 1.8V at 1.8V VCC
- 1.5V(1) to 2.5V at 2.5V VCC
- 1.8V(1) to 3.3V at 3.3V VCC
- 3.3V to 5.0V at 5.0V VCC
- Down translation:
- 3.3V to 1.8V at 1.8V VCC
- 3.3V to 2.5V at 2.5V VCC
- 5.0V to 3.3V at 3.3V VCC
- Logic output is referenced to VCC
- Output drive:
- 8mA output drive at 5V
- 7mA output drive at 3.3V
- 3mA output drive at 1.8V
- Characterized up to 50MHz at 3.3V VCC
- 5V Tolerance on input pins
- –40°C to 125°C operating temperature range
- Pb-free packages available: SC-70 (DCK)
- 2 × 2.1 × 0.65mm (height 1.1mm)
- Latch-up performance exceeds 250mA per JESD 17
- Supports standard logic pinouts
- CMOS output B compatible with AUP1G and LVC1G families (1)
(1)Refer to the VIH/VIL and output drive for lower VCC condition.
The SN74LV1T32 is a single 2-input OR gate with reduced input thresholds to support voltage translation applications.
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檢視所有 5 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | SN74LV1T32 Single Power Supply 2-Input Positive OR Gate CMOS Logic Level Shifter datasheet (Rev. D) | PDF | HTML | 2024年 5月 21日 |
| Application note | LV1T Family of single supply translators (Rev. B) | PDF | HTML | 2022年 12月 16日 | |
| Selection guide | Voltage Translation Buying Guide (Rev. A) | 2021年 4月 15日 | ||
| Application note | Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) | 2015年 4月 30日 | ||
| Application note | Selecting the Right Level Translation Solution (Rev. A) | 2004年 6月 22日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組
靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南: PDF
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOT-23 (DBV) | 5 | Ultra Librarian |
| SOT-SC70 (DCK) | 5 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點