產品詳細資料

Function Counter Bits (#) 12 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Function Counter Bits (#) 12 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6 SOP (NS) 16 79.56 mm² 10.2 x 7.8 SSOP (DB) 16 48.36 mm² 6.2 x 7.8 TSSOP (PW) 16 32 mm² 5 x 6.4 TVSOP (DGV) 16 23.04 mm² 3.6 x 6.4 VQFN (RGY) 16 14 mm² 4 x 3.5
  • 2V to 5.5V VCC operation
  • Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) 2.3V at VCC = 3.3V, TA = 25°C
  • Support mixed-mode voltage operation on all ports
  • High on-off output-voltage ratio
  • Low crosstalk between switches
  • Individual switch controls
  • Extremely low input current
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • 2V to 5.5V VCC operation
  • Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) 2.3V at VCC = 3.3V, TA = 25°C
  • Support mixed-mode voltage operation on all ports
  • High on-off output-voltage ratio
  • Low crosstalk between switches
  • Individual switch controls
  • Extremely low input current
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, class II

The ’LV4040A devices are 12-bit asynchronous binary counters with the outputs of all stages available externally.

The ’LV4040A devices are 12-bit asynchronous binary counters with the outputs of all stages available externally.

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* Data sheet SN74LV4040A 12-Bit Asynchronous Binary Counters datasheet (Rev. K) PDF | HTML 2024年 9月 4日

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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

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14-24-NL-LOGIC-EVM — 適用於 14 針腳至 24 針腳無引線封裝的邏輯產品通用評估模組

14-24-NL-LOGIC-EVM 是一款靈活的評估模組 (EVM),設計用途可支援任何具有 14 針腳至 24 針腳 BQA、BQB、RGY、RSV、RJW 或 RHL 封裝的邏輯或轉換裝置。

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模擬型號

SN74LV4040A IBIS Model

SCEM149.ZIP (16 KB) - IBIS Model
參考設計

TIDA-010005 — 軟體可配置心臟節律器偵測模組參考設計

This reference design implements a compact hardware-based circuit to detect the pacemaker pulse during ECG measurement. It provides indication of valid pace signal through a flag and onboard LED. This design enables the user to configure various parameters of the pace signal (amplitude, rise time, (...)
Design guide: PDF
電路圖: PDF

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  • 認證摘要
  • 進行中持續性的可靠性監測
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