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SN74LV4T00

現行

1.8V 至 5.5V 單電源供電四路 NAND 閘

立即訂購
產品規格表

SN74LV4T00

現行
產品規格表 立即訂購

產品詳細資料

Technology family LVxT Number of channels 4 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 15 IOH (max) (mA) -80 IOL (max) (mA) 8 Features Over-voltage tolerant inputs, Single supply, Voltage translation Input type TTL-Compatible CMOS Output type Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 125
Technology family LVxT Number of channels 4 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 15 IOH (max) (mA) -80 IOL (max) (mA) 8 Features Over-voltage tolerant inputs, Single supply, Voltage translation Input type TTL-Compatible CMOS Output type Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4 WQFN (BQA) 14 7.5 mm² 3 x 2.5
  • Wide operating range of 1.8 V to 5.5 V

  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):

    • Up translation:

      • 1.2 V to 1.8 V

      • 1.5 V to 2.5 V

      • 1.8 V to 3.3 V

      • 3.3 V to 5.0 V

    • Down translation:

      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5-V tolerant input pins
  • Supports standard pinouts
  • Up to 150 Mbps with 5-V or 3.3-V V CC
  • Latch-up performance exceeds 250 mA per JESD 17
  • Wide operating range of 1.8 V to 5.5 V

  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):

    • Up translation:

      • 1.2 V to 1.8 V

      • 1.5 V to 2.5 V

      • 1.8 V to 3.3 V

      • 3.3 V to 5.0 V

    • Down translation:

      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5-V tolerant input pins
  • Supports standard pinouts
  • Up to 150 Mbps with 5-V or 3.3-V V CC
  • Latch-up performance exceeds 250 mA per JESD 17

The SN74LV4T00 contains four independent 2-input NAND Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ● B in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

The SN74LV4T00 contains four independent 2-input NAND Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ● B in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
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* Data sheet SN74LV4T00 Quadruple 2-Input Positive-NAND GatesWith Integrated Translation datasheet PDF | HTML 2023年 4月 28日

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