封裝資訊
封裝 | 針腳 VSSOP (DCU) | 8 |
操作溫度範圍 (°C) -40 to 125 |
包裝數量 | 運送業者 250 | SMALL T&R |
SN74LVC2G02 的特色
- Available in the Texas Instruments
NanoFree™ package - Supports 5-V VCC operation
- Inputs accept voltages to 5.5 V
- Max tpd of 4.9 ns at 3.3 V
- Low power consumption, 10-µA Max ICC
- ±24-mA Output drive at 3.3 V
- Typical VOLP (output ground bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (output VOH
undershoot)
>2 V at VCC = 3.3 V, TA = 25°C - Ioff supports partial-power-down mode operation
- Latch-up performance exceeds 100 mA er JESD 78, class II
- ESD protection exceeds JESD 22
- 2000-V Human-body model (A114-A)
- 1000-V Charged-device model (C101)
SN74LVC2G02 的說明
This dual 2-input positive-NOR gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G02 device performs the Boolean function Y = A + B or Y = A × B in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.