SN74LVC3GU04

Name: SN74LVC3GU04
Brand: TI
SKU: SN74LVC3GU04
Price: 0.225 USD

現行

3 通道、1.65-V 至 5.5-V 逆變器

立即訂購

產品規格表

document-pdfAcrobat Triple Inverter Gate, SN74LVC3GU04 datasheet (Rev. D) (英文)

SN74LVC3GU04

現行

產品規格表

立即訂購

產品詳細資料

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Number of channels

IOL (max) (mA)

IOH (max) (mA)

-32

Supply current (max) (µA)

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Unbuffered, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Number of channels

IOL (max) (mA)

IOH (max) (mA)

-32

Supply current (max) (µA)

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Unbuffered, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

SSOP (DCT)

11.8 mm² 2.95 x 4

VSSOP (DCU)

6.2 mm² 2 x 3.1

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 3.9 ns at 3.3 V
Low Power Consumption, 10-μA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
Ioff Support Live Insertion, Partial Power Down Mode and Back Drive Protection
Unbuffered Outputs
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 3.9 ns at 3.3 V
Low Power Consumption, 10-μA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
Ioff Support Live Insertion, Partial Power Down Mode and Back Drive Protection
Unbuffered Outputs
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This triple inverter is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC3GU04 contains three inverters with unbuffered outputs and performs the Boolean function Y = A.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This triple inverter is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC3GU04 contains three inverters with unbuffered outputs and performs the Boolean function Y = A.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

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現行

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	類型	標題	日期
*	Data sheet	Triple Inverter Gate, SN74LVC3GU04 datasheet (Rev. D)	2013年 12月 23日
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