TLC3545
- 200-KSPS Sampling Rate
- Built-In Conversion Clock
- INL: ±1 LSB Max
DNL: ±1 LSB Max - SINAD = 81.5 dB, SFDR = 95 dB
THD = 94 dB at 15 kHz fin, 200 KSPS - SPI/DSP-Compatible Serial Interfaces With SCLK Input up to 15 MHz
- Single 5-V Supply
- Rail-to-Rail Analog Input With 500 kHz BW
- Two Input Options Available:
- TLC3541 – Single Channel Input
- TLC3545 – Single Channel, Pseudo-Differential Input
- (TLC3541) Optimized DSP Interface – Requires FS Input Only
- Low Power With Auto-Power Down
- Operating Current: 3.5 mA
- Auto-Powerdown Current: 5 uA
- Pin Compatible 12-/14-/16-Bit Family in 8-Pin SOIC and MSOP Packages
- APPLICATIONS
- ATE System
- Industrial Process Control
- Measurement
- Motor Control
The TLC3541 and TLC3545 are a family of high performance, 14-bit, low power, miniature CMOS analog-to-digital converters (ADCs). These devices operate from a single 5-V supply. Devices are available with single, dual, or single pseudo-differential inputs. All of these devices have a chip select (CS)\, serial clock (SCLK), and serial data output (SDO) that provides a direct 3-wire interface to the serial port of most popular host microprocessors (SPI interface). When interfaced with a DSP, a frame sync signal (FS) is used to indicate the start of a serial data frame on either pin 1 (CS)\ or pin 7 (FS) for the TLC3541. The TLC3545 ADC connects to the DSP via pin 1 only (CS)\.
The TLC3541 and TLC3545 are designed to operate with low power consumption. The power saving feature is further enhanced with an auto-power down mode. This product family features a high-speed serial link to modern host processors with an external SCLK up to 15 MHz. Both families use a built-in oscillator as the conversion clock, providing a 2.67 us maximum conversion time.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | 5-V, Low Power, 14-Bit, 200 KSPS, Serial ADC with Auto-Power Down datasheet | 2001年 5月 23日 | |
| E-book | Best of Baker's Best: Precision Data Converters -- SAR ADCs | 2015年 5月 21日 | ||
| Application note | Determining Minimum Acquisition Times for SAR ADCs, part 2 | 2011年 3月 17日 |
設計與開發
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5-6KINTERFACE — 5-6K 介面評估模組
The interface board consists of two signal conditioning sites, two serial EVM sites, and a parallel EVM site. Regardless of the interface type, all EVMs compatible with the 5-6K Interface Board have a standard analog interface and standard power connector. Three position screw terminals J1 and J2 (...)
ANALOG-ENGINEER-CALC — 類比工程師計算機
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
| VSSOP (DGK) | 8 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。