TPS51463
- Integrated FETs Converter w/TI Proprietary D-CAP+ Mode Architecture
- Minimum External Parts Count
- Support all MLCC Output Capacitor and SP/POSCAP
- Auto Skip Mode
- Selectable 700-kHz and 1-MHz Frequency
- Small 4 mm × 4 mm, 24-Pin, QFN Package
The TPS51463 is a fully integrated synchronous buck regulator employing D-CAP+™. It is used for up to 5-V step-down where system size is at its premium, performance and optimized BOM are must-haves.
The TPS51463 fully supports the Intel Chief River platform, a ULV/CPU system agent application with integrated 2-bit VID function.
The TPS51463 also features two switching frequency settings (700 kHz and 1 MHz), skip mode, pre-bias startup, programmable external capacitor soft-start time/voltage transition time, output discharge, internal VBST Switch, 2-V reference (±1%), power good and enable.
The TPS51463 is available in a 4 mm × 4 mm, 24-pin, QFN package (Green RoHs compliant and Pb free) and is specified from -40°C to 85°C.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | 3.3-V/5-V Input, D-CAP+™ Mode Synchronous Step-Down Integrated FETs Converter datasheet | 2012年 1月 26日 |
設計與開發
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TPS51463 Unencrypted PSpice Transient Model Package (Rev. A)
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
VQFN (RGE) | 24 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點