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CCD AFE Block Diagram Descriptions

Clamp

The output of the CCD sensor has a large DC offset. Therefore, the CCD output is capacitively coupled to the AFE. The AC coupling capacitor is clamped to establish proper DC bias during the dummy pixel interval by this block. The bias at the input to the AFE is set to 1.2V. Normally, this occurs at the sensor’s line rate. A capacitor, with a value ten times larger than that of the input AC coupling capacitor, should be connected between the clamp reference pin (normally CLREF) pin and the analog ground node.

CDS

The correlated double sampler (CDS) function is used to eliminate the kT/C noise as well as much of the 1/f and white noise inherent to the CCD output signal. This noise reduction is accomplished by sampling the CCD output signal twice and using the difference between these two samples for the actual "image information." First the CCD signal reference level is sampled and held (SR) at the end of the reset period of the signal for each pixel. The opening of the reset switch causes the dominating kT/C noise essentially to "freeze" in its last point. The second sample and hold (SV) function occurs at the peak of the video portion of the signal for each pixel. The difference between the two samples is ideally equal to a voltage (DV) corresponding to the transferred charge signal. During some period of operation, large transients may occur at the AFE’s input, which can saturate the input circuits and cause long recovery time. To prevent the circuit saturation under such situation, the AFE includes an input blanking function that blocks the input signals by disabling the CDS operation whenever this control (usually called BLKG) input is pulled low.

PGA

The Programmable Gain Amplifier (PGA) is used to adjust the signal level coming out of the CCD to maximize the dynamic range used by the ADC. The signal is sent to the PGA after the CDS function is complete. The PGA gain can be adjusted from 0 to 36 dB by programming the internal gain register via the serial port. The PGA is digitally controlled with 9-bit resolution on a linear dB scale, resulting a 0.09 dB gain step. The ideal gain curve can be expressed by the following equation:

Gain (dB) = PGA code ? 0.09375 dB + Gain offset ;Where:
PGA code has a range of 0 to 384
Gain offset = 0.1 dB.

The PGA serves the same function as an AGC amplifier. However a PGA exhibits superior linearity over a analog controlled AGC . The chart shows the actual data measured on one of TI’s AFE devices.

ADC

The Analog–to–Digital Conveter (ADC) employs a pipelined architecture to achieve high throughput and low power consumption. Fully differential implementation and digital error correction ensure 10-bit resolution. The latency of the ADC data output is 4.5 ADCCLK cycles as shown.

OBC

In the AFE, the optical black and system channel offset corrections are performed by an auto digital feadback loop. Two DACs are used to compensate for both channel offset and the optical black offset. A coarse correction DAC (CDAC) is located before PGA gain stage and a fine correction DAC (FDAC) is located after the gain stage. The digital calibration system is capable of correcting the optical black and channel offset down to one ADC LSB accuracy.

The AFE automatically starts the auto–calibration whenever the contol input is pulled low, the pulse should be wide enough to cover one positive half cycle of the converter clock.

For each line, the optical black pixels plus the channel offset are sampled and converted to digital data by the ADC. A digital circuit averages the data during the optical black pixels. The final averaged result is compared digitally with the desired output code stored in the black level register (Vb), then control logic adjusts the FDAC to make the ADC output equal to Vb. If the offset is out of the range of the FDAC (?255 ADC LSBs), the error is corrected by both CDAC and FDAC. The CDAC increments or decrements by one CDAC LSB depending on whether the offset is negative of positive, until the output is within the range of the FDAC. The remaining residue is corrected by the FDAC.

The relationship among the FDAC, CDAC, and ADC in terms of number of ADC LSBs is as follows,

1 FDAC LSB = 1 ADC LSB,
1 CDAC LSB = 0.5 x PGA linear gain ? 1 ADC LSB.

For example, if PGA gain = 2 (6dB), then, 1 CDAC LSB = 1 ADC LSB.

After the auto-calibration is complete, the ADC’s digital output during CCD signal (non optical black) interval can be expressed by the following equation,

ADC output [D9-D0] = CCD_input ? PGA gain + Vb,

The number of black pixels in each line and number of lines are programmable. The number of black pixels per line that can be averaged equals to 2N, where N can be 0, 1, 2, 3, 4, 5, and 6. In addition there is an additional control bit which can be used to set the number of plack pixels to 3 x 2N. The number of lines equals to 2L, where L can be 0, 1, 2, 3, 4, 5, 6, 7, and 8.

The auto-calibration feature can be bypassed if the user prefers to directly program the offset DAC registers. Switching the auto-calibration mode to the direct programming mode requires two register writes. First, the control bits for the offset DACs in the control register needs to be changed then desired offset value for the register is loaded to the offset DAC registers for proper error correction. If the total offset including optical black level is less than ?255 ADC LSBs, only the FDAC needs to be programmed. When switching from the direct programming mode to the auto-calibration mode, the previous DAC register values are used as starting offsets rather than default DAC register values.

A detailed block diagram for the internal automatic optical black and offset correction is shown. The timing diagram illustrates the operation of the calibration system. In the example, the AFE is programmed to average four black pixels (N=2) per line for two lines (L=1).

To avoid the ADC being clipped on differential negative input signals, an internal offset that equals to 255 ADC LSBs is intentionally added to the PGA output signal. This offset is only added during optical black pixel interval with a total duration of 2N + 3 pixels, where three additional pixels are necessary for accommodating internal latency adjustment.

Serial Port

The serial port consists of a s simple 3-wire (SCLK, SDIN, and CS) interface. It is provided to allow writing to the internal registers of the AFE. The serial clock SCLK can be run at a maximum speed of 40 MHz. The serial data SDIN is 16 bits long. After two leading null bits, there are four address bits for which internal register is to be updated, the following ten bits are the data to be written to the register. To enable the serial port, the CS pin must be held low. The data transfer is initiated by the incoming SCLK after the CS falls.

2 User DACs

TI’s AFEs include two user DACs that can be used for external analog settings. The output voltage of each DAC can be independently set and has a range of 0V to the supply voltage with 8-bit resolution. The values are set by programming the control registers via the serial port. When the user DACs are not used in a camera system, they can be put in the standby mode by programming control bits in the control register.

Voltage Refs

An internal precision voltage reference (bandgap reference) of 1.5V nominal is provided. This reference voltage is used to generate the ADC Ref- voltage of 1V and Ref+ of 2V. It is also used to set the clamp voltage. All internally generated voltages are fixed values and cannot be adjusted. These three signals; bandgap reference, ADC Ref+, and ADC Ref-; must be decoupled to analog ground.