Our integrated circuits and reference designs help you create campus and branch switches with higher bandwidth and low power consumption. Use the interactive reference diagram below to design modern, high-speed campus and branch switches to support the connectivity needs of today's Ethernet switch fabric with our power-over-Ethernet (POE), microcontroller, interface, physical interface device (PHY) and power management products.
Modern campus and branch switches require:
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| Type | Title | Date | ||
|---|---|---|---|---|
| Application note | How to use the LMK05318 as a jitter cleaner | 27 Feb 2019 | ||
| Application note | Glitch free power sequencing with AXC level translators (Rev. A) | 20 Sep 2018 | ||
| Application note | Interfacing Between LVPECL, VML, CML and LVDS Levels | 16 Dec 2002 | ||
| Application note | Supported synchronization modes for TI network synchronizers (Rev. A) | 11 May 2022 | ||
| Application note | DC/DC Point-of-load Power Solutions for Wired Networking Switch Systems | 11 May 2022 | ||
| Application note | Understanding clocking needs for high-speed 56G PAM-4 serial links (Rev. A) | 11 May 2022 | ||
| Application note | Optimizing Network Switch Designs with Common Logic Use Cases (Rev. A) | PDF | HTML | 10 May 2022 | |
| Analog Design Journal | Understanding thermal-resistance specification of DC/DC convert. w/ MOSFETs | 08 Jan 2018 | ||
| White paper | Internally compensated advanced current mode (ACM) (Rev. A) | 07 Dec 2018 | ||
| Analog Design Journal | Comparing internally-compensated advanced current mode (ACM) w/ D-CAP3™ control (Rev. A) | 06 Nov 2018 |
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