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Precision labs series: Analog-to-digital converters (ADCs)

These on-demand courses and tutorials include introductory ideas about device architecture in addition to advanced, application-specific problem-solving, using both theory and practical knowledge. Industry experts present each topic in order to help reduce design time and move quickly from proof-of-concept to productization. The ADC (analog-to-digital converter or A/D converter) curriculum is segmented into major topic learning categories, each of which contains short training videos, multiple choice quizzes and short answer exercises.

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      Hello. And welcome to the TI Precision Lab series introducing the basic operation of SAR and Delta Sigma converters. The objective of this content is to give a very high-level understanding of how the two topologies work. This overview, in conjunction with subsequent videos, should help you decide which topology is best for your application.

      This slide provides a basic summary of the advantages and disadvantages of each topology. Notice that the Delta Sigma topology is separated into DC optimized and wide bandwidth subcategories. This distinction was made because the advantages, disadvantages, and usage considerations are very different for the two different types of Delta Sigma converters. Unfortunately, this distinction is not directly stated in the data sheet. And you need to infer the difference by looking at the internal digital filter type and the device sampling rate.

      From an applications' perspective, the wide bandwidth Delta Sigma behaves closer to a SAR converter. Let's take a closer look at each category. First, the SAR converter is most commonly used to capture a snapshot in time for a transient signal.

      Also, SAR converters have the advantage of low latency. Latency is the delay between when the input signal is applied and the output conversion is available. We will discuss latency in more detail later in this presentation series.

      The wide band Delta Sigma has many similar characteristics to the SAR, except that they frequently will have a noise and resolution advantage. On the other hand, the wide bandwidth Delta Sigma has the disadvantage of higher latency than a SAR. Finally, the DC optimized Delta Sigma converters are designed to measure very low bandwidth signals. These ADCs have internal digital filters that subsequently limit the bandwidth and reduce the noise. This category of converters typically has low latency compared to the wide bandwidth Delta Sigma converter.

      This brief introduction is just a preview of the content that will be covered in the next few videos. In this video, we will cover the basic internal mechanisms used to convert voltage in a SAR and Delta Sigma converter. A very simple block diagram of a SAR converter is shown here.

      The switch, RSH, CSH form the sample and hold circuit. When the switch is closed, the sample and hold circuit will charge up to the input signal VN. When the switch opens, the voltage on the capacitor will maintain or hold the voltage sampled in the previous step.

      While the voltage is held, the converter will translate this voltage into a conversion result. The conversion is done in multiple steps by adjusting the output of the CDAC during each step and comparing it to the held voltage. In fact, the acronym SAR stands for Successive Approximation Register.

      The name refers to the process where CDAC is adjusted in successive approximations to try and match the voltage stored in the sample and hold. The word register refers to the fact that the result for each conversion step is stored in a register. Let's consider an analogy to help clarify the SAR operation.

      So how does a SAR ADC work? Consider the SAR to be like a balanced weight scale where the input voltage is an unknown weight. On the right side, we have several calibrated counterbalance weights. These weights are scaled in binary.

      And since we have three counterweights, this essentially represents a three-bit converter. The first step to making the measurement is to apply the unknown weight to the left-hand side of the scale. This is analogous to the sampling period, also called the acquisition period, of a SAR ADC.

      Next, we begin adding the calibrated counterbalance weights starting with the heaviest weight. This is analogous to testing the most significant bit or MSB in a conversion. You can see, in this example, that the unknown quantity is heavier than the counter weight. So it is kept on the scale, and the MSB value is assigned to a binary one.

      In the next step, we add the 1/2 counterweight and notice that the counterweights combined exceed the unknown value. In the last step, we apply the 1/4 counterweight and notice that the scale is balanced. Thus, the 1/4 weight will remain on the scale. And the binary equivalent of the unknown weight is 1 0 1.

      In this analogy, the sample and hold is the left-hand side of the scale. The balance point is the comparator. And the calibrated counterweights are the CDAC output.

      Now let's revisit the actual circuit and look deeper into some of the details. Previously, we mentioned that the switch and RC circuit formed the sample and hold for the ADC. The period where the switch is closed and the ADC is sampling is called the acquisition cycle for the ADC.

      The length of this period depends on the sampling rate of the converter and will be given in the data sheet. For example, the ADS 8860 has an acquisition period of 290 nanoseconds for a sampling rate of 1 mega sample per second. During the acquisition period, the voltage applied to the input needs to charge up the internal capacitor, CSH.

      Since this is an RC circuit, the capacitor will charge at an exponential rate, as shown in the graph on the left. For best accuracy, the sample and hold must be designed to charge within 1/2 LSB of the input voltage. The 1/2 LSB is the maximum error that will not be detected by the ADC, as it is smaller than the ADC's resolution.

      The process of selecting the best external components to assure that the settling error is minimized is covered in detail in a later Precision Lab series. After the acquisition period, the ADC begins to convert the sampled signal. It does this by adjusting the CDAC to try and match the voltage stored on the sample and hold the capacitor, CSH.

      Each time the CDAC is adjusted, one bit in the conversion result is calculated. Thus, a 12-bit converter will adjust the CDAC 12 times. The result of each successive approximation is stored in the N-bit register.

      This diagram shows the conversion cycle for a five-bit converter. In this example, the analog input voltage, which is stored on CSH, is shown by a green dotted line. The CDAC output is shown by a red line and always starts with the heaviest bit weight, the MSB.

      This bit weight will be equal to 1/2 of the full scale range. As we step through the successive conversion steps, we will keep on any DAC output that does not exceed the analog input. And we will turn off any DAC output that does exceed the analog input.

      Let's step through the conversion. The MSB does not exceed the analog input. So we keep this bit and set its binary value to one. The next bit test, MSB minus one, does exceed the analog input.

      So this one is turned off. And its equivalent is a binary zero. The MSB minus two test does not exceed the analog input. So it is kept on and has a binary value of one. The last two bits both exceed the analog input, and they are turned off and have binary equivalents of zero. Thus, the overall conversion result for this example is 10100.

      In following videos, we will revisit this simplified view of the SAR ADC and use it to help with input drive and voltage reference drive topics. This figure compares the SAR conversion method on the left to the Delta Sigma conversion method on the right. The points in time where the SAR sample and hold captures the signal are shown with the red dots.

      People often refer to the SAR conversion as a snapshot because the sample and hold circuit freezes this voltage level during the hold period similar to the way that a camera captures a picture when the shutter snaps. The Delta Sigma converter, on the other hand, has more of an averaging effect over a fixed time interval. Looking at the figure on the right, you can see that each green interval indicates the conversion period for the Delta Sigma.

      At the end of the conversion period, the conversion result is calculated as an average value of the signal across the interval. This average value is represented by a red dot in this figure. Of course, saying that the Delta Sigma simply averages across this time interval is an oversimplification. For the remainder of this video, we will provide more details about the internal operation of the Delta Sigma converter. These details will help you to better understand the advantages and disadvantages of this topology as well as give you insight into their datasheet specifications.

      Let's start by considering a very simplified model of a Delta Sigma ADC. One key point to remember with the Delta Sigma is that the input circuit, called the modulator, is sampling at a faster rate than the output data rate. In this example, the modulator is sampling at a one mega sample per second rate. Note that the modulator clock is derived from an external master clock. In this example, the external master clock is running at a rate of 16.384 megahertz and is divided down to a rate of one megahertz for the modulator.

      The conversion results from the modulator are averaged and filtered by a digital filter. The output data rate is always lower than the modulator sampling rate. In this example, the modulator is sampling at one megahertz. And the output data rate is only 60 hertz or 60 samples per second. Thus, for each day the word read at the output of the converter, 16,000 input samples are averaged together.

      The ratio of the modulator rate divided by the output data rate is called the Oversampling Ratio, or OSR. In this example, the OSR is 16,000. We will focus on the operation of the Delta Sigma converter for the remainder of this presentation.

      The simplified model on the previous page can be redrawn like this block diagram. Starting on the left, the analog input signal is applied to the modulator. The modulator essentially behaves like a one-bit converter and converts the analog input to a pulse code modulated or PCM signal.

      This PCM signal is applied to a digital filter, which uses averaging to convert this bit stream to a higher resolution signal. The decimeter eliminates samples, such that, the output data rate is a fraction of the input data rate. Again, if the input is averaged 16,000 times, the decimeter will output one sample for every 16,000 input samples.

      A large oversampling ratio indicates that a lot of averaging has been done to the signal. Oversampling reduces noise and increases output resolution. To understand more details on the modulator and digital filter, we first must cover a very short explanation of quantization noise and oversampling.

      The objective here is to briefly introduce these topics to help with the explanation of the Delta Sigma topology. And in later videos, we'll do a more comprehensive discussion on these topics. First, let's discuss the concept of quantization noise.

      All data converters will round the analog input signal to discrete digital levels. This process is referred to as quantizing the signal. And the associated error is called quantization error.

      If you apply an AC sine wave to an analog to digital converter, the resultant digitized waveform will have an error that looks like a sawtooth waveform versus time. The FFT of that sawtooth waveform will produce harmonics across a wide frequency range. And the harmonics will alias back into the Nyquist frequency band.

      The result is that the noise floor appears like white noise. In fact, the Signal to Noise Ratio, or SNR, due only to quantization noise can be mathematically predicted with the equation SNR expressed in decibels is equal to 6.02 times n plus 1.76, where n is the number of bits in the converter. Note that this equation only applies to a pure sinusoidal wave input. The important thing to note here is that the noise floor of an ideal analog to digital converter is determined only by the quantization noise.

      When sampling a signal at discrete intervals, the Nyquist-Shannon sampling theorem states that the sampling frequency, fs, must be greater than twice the highest frequency component of the input signal in order to reconstruct the original signal from the sampled version. This minimum sampling rate is known as the Nyquist rate. In later videos, we will discuss the concept of aliasing in more detail. But for now, just realize that our usable frequency range is from DC to the sampling frequency divided by two, also known as the Nyquist frequency.

      Applying an input signal beyond the Nyquist frequency will cause aliased frequencies to fold back into the Nyquist frequency band. Most ADCs sampled had frequencies close to the Nyquist rate. The quantization noise for an ADC with n bit resolution is evenly distributed over the sampled bandwidth between DC and the Nyquist frequency.

      The Signal to Noise Ratio, or SNR, for an ideal ADC is given by the equation SNR expressed in decibels is equal to 6.02 times n plus 1.76, where n is the number of bits. The oversampling FFT plot on the right shows the effect of oversampling. The input signal frequency is the same. But the sampling frequency has been increased by an oversampling ratio k.

      Oversampling increases the bandwidth considerably. Hence, it spreads the quantization noise over a wider bandwidth. The quantization noise power remains constant. But the quantization noise is now spread over a higher sampled bandwidth from DC to k times fs divided by two.

      It is important to realize that the total amount of noise power remains the same. But the noise has been spread over a wider frequency range. And the noise level in each frequency bin in the FFT has been reduced.

      A digital low-pass filter can be used to eliminate the high frequency noise while keeping the input frequency signals of interest. In this example, the digital filter in the oversampling example has the same bandwidth as the Nyquist sampling example. The digital filter retains a small amount of noise and rejects the noise outside the filter's bandwidth.

      In this manner, oversampling can be used to increase resolution. After filtering the high frequency components, the ideal SNR can now be calculated by the equation SNR in db is equal to 6.02 times n plus 1.76 plus 10 times the log of the OSR, where the OSR is the Oversampling Ratio. The term 10 times the log of OSR is the noise improvement gained from the oversampling.

      Notice that both formulas are the same, except for this term. With the concepts of quantization noise and oversampling in mind, let's return to this slide, which illustrates the internal Delta Sigma signal chain. The main purpose of the modulator is to convert an analog input to a Pulse Code Modulation output, or PCM.

      Pulse code modulation is a bit stream where the average value is proportionate to the analog input. So for small analog inputs, the PCM bit stream is mostly zeros. And for a large analog input, the bit stream is mostly ones. In this example, the modulator is running at a one mega sample per second frequency. So the PCM bit stream is also output at that rate.

      In the next slide, we'll take a closer look at the modulator and a PCM example. This slide shows a pulse code modulation example. Note that the occurrence of ones and zeros relates to the analog input. For low analog input levels, the PCM bits will be mostly logic zeros. And for high analog input levels, the PCM bits will be mostly logic ones.

      Averaging the PCM bit stream is done by adding the ones and zeros and dividing by the number of bits averaged. If we consider the example from the last slide, 16,000 bits would be averaged to produce one output sample. Also, the frequency of the digital output bit stream is the frequency that the modulator is running at. So this bit stream would be output at a rate of one megahertz.

      Now let's take a closer look at how the modulator converts its analog input to a PCM output. This slide shows the block diagram internal to the modulator. This is a control system style diagram.

      The objective of this control loop is to keep the error between the analog input and digital output as small as possible. In order to compare the analog input to the digital output, the output is converted back to analog with a one-bit digital to analog converter. This is shown in the feedback loop and the input error summing block.

      The error from the input summing block is integrated, as is commonly done in many control systems. As the output of the integrator gets larger, the comparator will trip the digital output to a logic one. This action will cause the error to go negative. And the integrator will then ramp in the opposite direction.

      Thus, the closed loop system will tend to keep the error minimized by periodically transitioning the output of the comparator to a one or a zero. If you average the ones and zeros after a long period of time, you will get a digital equivalent of the analog input. As with many of the explanations here, this is an oversimplification. However, this description should give you some intuition into how the Delta Sigma modulator operates, which will be helpful in interpreting the data sheet and comparing and contrasting other converters.

      This block diagram of the Delta Sigma modulator shows the input signal and noise transfer function in the frequency domain. Analyzing the transfer function, you can see that the output is fed back and subtracted from the input signal. Assume that the one-bit DAC is essentially a gain of one. Thus, the output of the summing block is VIN minus DOUT. This is then multiplied by the integrator with a gain of 1/f.

      Finally, the quantization noise term is added to the output summing block. This is where we get the first equation. DOUT is equal to VIN minus DOUT times 1/f plus e sub n. Notice that DOUT is on both sides of the equation. Solving for DOUT with some algebra, you can get the second equation.

      Looking closely at the second equation, the noise is multiplied by a high-pass filter. And the input voltage is multiplied by a low-pass filter. This result has very important implications into understanding how a Delta Sigma ADC operates. First, note that applying the input signal to a low-pass filter means that the desired signal will pass through the modulator. But higher frequency noise signals will be limited.

      Next, notice that multiplying the quantization noise by the high-pass filter shapes the noise. It effectively minimizes the noise at low frequencies and does not attenuate the noise at high frequencies. Later, we will see that a digital filter will be applied to the modulator output to eliminate the high frequency noise.

      This example shows a modulator with a first order integration. Some Delta Sigma converters will use higher order integrations. In the next slide, we will look at how higher order modulators impact the noise shaping for a Delta Sigma converter.

      This diagram shows the spectral noise densities for first, second, and third order modulators, all with the sampling frequency of fs. Higher order modulators can be used to get better SNR at lower data rates. This is because the higher order modulator shifts more of the noise to high frequencies and reduces the quantization noise near the signals of interest.

      If you look at this example, you can see that the third order modulator, shown in blue, is the lowest noise near the signal of interest because that noise was shifted to high frequencies. Later, we will see that the noise at high frequencies is not important, as it will be filtered out by a low-pass digital filter in the next stage. Before we look at the digital filter, let's review what the input and output of the modulator look like in both the time and frequency domain.

      Here is what the signal looks like at the output of the modulator in the time and frequency domain. The time domain signal is a pulse code modulation bit stream. If this signal is averaged, it would equal the value of the input signal. The PCM signal is applied to a digital filter, which will perform the averaging function and will also impact the frequency domain response.

      The frequency domain plot shows the effective noise shaping. Notice that the noise near the input signal is low, while the noise is higher at high frequencies. Let's review the block diagram again.

      In this diagram, you can see that the PCM bit stream from the modulator is applied to the digital filter and decimeter. The digital filter will average the bit stream to effectively recreate the analog signal as a high resolution result. Remember that the process of oversampling averages many modulator samples to produce one high resolution output sample.

      The digital filter is also used to filter the high frequency noise from the modulator output. The filter is followed by the decimeter block, which limits the number of samples at the output according to the oversampling ratio. Let's look more closely at how the digital filter minimizes the modulator noise.

      This slide shows the quantization noise shaped at the output of the modulator. Notice that the noise is minimal near the signal of interest. Adding a digital filter will eliminate the large noise at higher frequencies. The noise that passes through the digital filter is minimal compared to the overall noise power.

      This example uses a sinc1 filter to eliminate the high frequency noise. Using a higher order filter will further reduce the noise. Here, we see a sinc2 filter. This filter rejects more noise than a sinc1, as it has a sharper pass band transition.

      This last example shows a sinc3 filter. This one reduces the noise even further. In general, choosing a higher order filter or reducing the cutoff frequency are two approaches to minimizing the quantization noise.

      For some practical DC optimized Delta Sigma converters, the cutoff frequency of this filter may be as low as a few hertz. For wideband Delta Sigma converters, the noise may be hundreds of kilohertz. If you compare the noise specifications between low and wide bandwidth Delta Sigma converters, you will see that the wider bandwidth device generally has more noise.

      That concludes the theory part of this video. Thank you for your time. Continue watching to try the quiz and check your understanding of this video's content.

      Question one, which ADC topology has an acquisition cycle and a conversion cycle? The answer here, of course, is, a, a SAR ADC. Question two, true or false, SAR ADCs use noise shaping and oversampling to reduce the quantization noise. The answer is false. Delta Sigma ADCs, not SAR ADCs, feature an integration stage to shape the noise and a digital filter to average the modulator output by the oversampling ratio.

      Question three, which ADC topology's conversion acts as a snapshot in time? The answer is, a, a SAR converter, which takes one sample at a time and converts the result. Final question, the modulator of a Delta Sigma converter is sampling at one megahertz. The data rate of the converter is 100 samples per second. What is the OSR? The answer is, d. One megahertz divided by 100 samples per second gives us an oversampling ratio of 10,000.

      Topics
      Expand all
      Understanding the difference between SAR and delta-sigma ADCs (4)
      ADC drive topologies (5)
      AC and DC specifications (7)
      ADC noise (16)

      Introduction to noise in ADC systems

      00:13:01

      Types of noise in ADCs

      00:15:44

      ADC noise measurement, methods and parameters

      00:25:34

      System noise performance for low-speed delta-sigma ADCs

      00:25:06

      Analyzing and calculating noise bandwidth in ADC systems – multi-stage filters

      00:24:37

      Analyzing and calculating noise bandwidth in ADC systems – the digital filter

      00:23:48

      Gain impact on noise, ADC FSR and dynamic range

      00:22:28

      Calculating amplifier + ADC total noise: design examples

      00:13:12

      Introduction to reference noise in ADC systems

      00:15:36

      Reference noise affect on signal chain performance

      00:17:55

      Reducing reference noise ADC systems: ratiometric, internal, external

      00:11:32

      How clocking noise affects precision ADC measurements

      00:22:34

      Understanding power supply noise in ADC systems

      00:12:23

      Power supply noise mitigation techniques

      00:13:16

      Calculating the total noise for ADC systems

      00:10:11

      Hands-on experiment: ADC noise

      00:16:35
      Error sources (3)
      Digital communications basics (6)
      SAR ADC input driver design (7)
      Driving the reference input on a SAR ADC (6)
      Protecting ADCs from electrical overstress (EOS) (12)
      PCB design for good EMC (8)
      Measuring RTDs with precision ADCs (11)
      Low-power SAR ADC system design (2)
      High-speed ADC fundamentals (7)
      View series

      Precision labs series: Analog-to-digital converters (ADCs)

      Expand all
      Understanding the difference between SAR and delta-sigma ADCs (4)
      ADC drive topologies (5)
      AC and DC specifications (7)
      ADC noise (16)

      Introduction to noise in ADC systems

      00:13:01

      Types of noise in ADCs

      00:15:44

      ADC noise measurement, methods and parameters

      00:25:34

      System noise performance for low-speed delta-sigma ADCs

      00:25:06

      Analyzing and calculating noise bandwidth in ADC systems – multi-stage filters

      00:24:37

      Analyzing and calculating noise bandwidth in ADC systems – the digital filter

      00:23:48

      Gain impact on noise, ADC FSR and dynamic range

      00:22:28

      Calculating amplifier + ADC total noise: design examples

      00:13:12

      Introduction to reference noise in ADC systems

      00:15:36

      Reference noise affect on signal chain performance

      00:17:55

      Reducing reference noise ADC systems: ratiometric, internal, external

      00:11:32

      How clocking noise affects precision ADC measurements

      00:22:34

      Understanding power supply noise in ADC systems

      00:12:23

      Power supply noise mitigation techniques

      00:13:16

      Calculating the total noise for ADC systems

      00:10:11

      Hands-on experiment: ADC noise

      00:16:35
      Error sources (3)
      Digital communications basics (6)
      SAR ADC input driver design (7)
      Driving the reference input on a SAR ADC (6)
      Protecting ADCs from electrical overstress (EOS) (12)
      PCB design for good EMC (8)
      Measuring RTDs with precision ADCs (11)
      Low-power SAR ADC system design (2)
      High-speed ADC fundamentals (7)