The CDCLVP2106 is a high-performance, low additive phase noise clock buffer. It has two universal input buffers that support either single-ended or differential clock input. Each input feeds a bank of six LVPECL outputs. The device also features on-chip bias generators that can provide the LVPECL common-mode voltage to the device inputs. This evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVP2106. This fully assembled and factory-tested evaluation board allows complete validation of the CDCLVP2106device functionalities. For optimum performance, the board is equipped with 50-ohm SMA connectors and well-controlled, 50-ohmimpedance microstrip transmission lines.
| Type | Title | Date | ||
|---|---|---|---|---|
| Certificate | CDCLVP2106EVM EU Declaration of Conformity (DoC) | 02 Jan 2019 | ||
| Data sheet | CDCLVP2106 12-LVPECL Output, High-Performance Clock Buffer datasheet (Rev. B) | PDF | HTML | 25 Oct 2013 | |
| EVM User's guide | Low Additive Phase Noise Clock Buffer Evaluation Board | 25 Aug 2009 |
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