This reference design uses only 2 ICs in a stacked configuration to provide 2.7 V at 60 A in a compact form factor. Both an all ceramics output capacitors version and a low ESR polymer output capacitors version were demonstrated to meet requirement of less than 3% undershoot for a step load from 2 A to 60 A in less than 1 microsecond. Internal compensation simplifies the design process. Design includes on-board high speed dynamic load tester, output ripple probe interface and test points for a stability analyzer.
| Output voltage options | PMP21619.1 |
|---|---|
| Vin (Min) (V) | 10 |
| Vin (Max) (V) | 14 |
| Vout (Nom) (V) | 2.7 |
| Iout (Max) (A) | 60 |
| Output Power (W) | 162 |
| Isolated/Non-Isolated | Non-Isolated |
| Input Type | DC |
| Topology | Multiphase |
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
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Test results for the reference design, including efficiency graphs, test prerequisites and more
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Detailed overview of design layout for component placement
Files used for 3D models or 2D drawings of IC components
Design file that contains information on physical board layer of design PCB
PCB layer plot file used for generating PCB design layout
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Test report | Dual-phase compact reference design for 2.7 V 60 A for telecommunications | Feb. 06, 2019 |
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