This circuit demonstrates the implementation of a low power, RS-485 transceiver with selectable data rate and flexible I/O logic levels. A dual-output LDO allows for operation with either 1.8V or 3.3V interface logic levels. A slew rate selection pin allows for driver slew rate control, enabling low-speed data transmission (250kbps) over long distances, or high-speed data transmission (20Mbps) over shorter bus lengths.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
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Test results for the reference design, including efficiency graphs, test prerequisites and more
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Design file that contains information on physical board layer of design PCB
| Type | Title | Date | ||
|---|---|---|---|---|
| Test report | TIDA-00193 Test Results | Mar. 25, 2014 |
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