CODELOADER
CodeLoader Software for device register programming
CODELOADER
Overview
The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.
Which software do I use?
Product | Loop filter & device configuration + simulation | Device register programming |
LMX24xx PLL family | EasyPLL | CodeLoader* |
LMX25xx PLL+VCO family | ||
LMK jitter cleaners and distributors |
*For new designs, use the Clocks and Synthesizers (TICS) Pro Software tool.
Downloads
Additional resources you might need
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
Supported products & hardware
Products
Clock generators
Clock buffers
Oscillators
Clock jitter cleaners
Clock network synchronizers
RF PLLs & synthesizers
Hardware development
Evaluation board
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICS Pro 1.7.7.9 installer binary for Windows operating system
Products
Clock generators
Clock buffers
Oscillators
Clock jitter cleaners
Clock network synchronizers
RF PLLs & synthesizers
Hardware development
Evaluation board
Documentation
TICS Pro 1.7.7.9 Release Notes
TICS Pro 1.7.7.9 Software Manifest
Release Information
NOTE: v1.7.7.8 was withdrawn due to the installer being built with an older version of several profiles. v1.7.7.9 includes the correct files, and is otherwise identical to v1.7.7.8.
Bug Fixes
- Start Page: dimming improvements for unused input references, force FB config 1 only and require manual copying for FB config 2
- Validation Page: DPLL LOFL validation registers for FB2 are programmed for cases where FB2 is used
- ZDM Page: Added relative time calculations for DPLLx_PH_OFFSET
- Programming Page: Added DPLL loop filter register generator, clearly indicate ROM-only registers for post-EEPROM boot sequence
- LMK5B12212 will now calculate loop filter values
- LMK5B12212 and LMK5C12212A "Read Status" and "Read RO Regs" buttons fixed
- LMK5B12212 and LMK5C12212A corrected PLL1 VCO post-divider frequency on OUT0&1, OUT2&3 pages
- Improved accuracy of frequency error warnings
- Frequency Planner: OUT0/OUT1 CMOS and LDO voltage are now correctly set, REFx for OUT0 or OUT1 is now correctly set
- ZDM configuration now fails more gracefully for unsupported non-integer input/output attempts
Known Issues
- NEW: LMK5B and LMK5C family - In some cases, "Assign Selected VCO Settings to Device" and "Apply Output Clock Settings to Device" may need to be pressed twice for certain cascaded configurations to display correctly
- LMK5C33216 - When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
- LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
PLLATINUMSIM-SW — PLLatinum Sim Tool
Supported products & hardware
Products
Clock buffers
Clock generators
Clock jitter cleaners
Clock network synchronizers
RF PLLs & synthesizers
IQ demodulators
Hardware development
Evaluation board
PLLATINUMSIM-SW — PLLatinum Sim Tool
Products
Clock buffers
Clock generators
Clock jitter cleaners
Clock network synchronizers
RF PLLs & synthesizers
IQ demodulators
Hardware development
Evaluation board
Documentation
Release Information
Bug fixes
What's new
- Fixed Kvco calculation bug introduced in 1.6.6
- Added warning for loop bandwidth being restricted due to min high order capacitance.
Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | User guide | CodeLoader 4 Operating Instructions User's Guide (Rev. A) | 21 Jul 2014 | |
Technical article | A survival guide to scaling your PLL loop filter design | PDF | HTML | 22 Nov 2016 | |
Technical article | What to do when your PLL does not lock | PDF | HTML | 12 Jul 2016 |
Support & training
TI E2E™ forums with technical support from TI engineers
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