CDC-CDCM7005-CALC

CDC7005 和 CDCM7005 PLL 迴路頻寬計算機

CDC-CDCM7005-CALC

概覽

This tool helps to determine the right divider values (M, N & P) and to choose the filter type and components. This calculator will help to find out the appropriate loop bandwidth, phase margin, jitter peaking, etc. just varying the loop parameters like PFD frequency, filter components, Charge pump current, and VCO gain (Hz/V). This is a software package that lets the Engineers enter a piecewise-linear noise model for the VCO (VCXO) and the reference clock source to predict the PLL output phase noise and hence calculate the phase jitter.

特點

The lab view based tool can:

  • Determine the PFD frequency automatically
  • Calculate loop bandwidth, Phase margin and Jitter peaking
  • Predict the PLL output Phase noise
  • Calculate Phase Jitter (rms)

技術文件

找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 1
類型 標題 下載最新的英文版本 日期
資料表 CDCM7005-SP 3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and Jitter Cleaner datasheet (Rev. G) PDF | HTML 2015/12/3

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

檢視所有論壇主題 以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援