Hello. My name is Lori Heustess. And I would like to welcome you to Concerto College. This is topic number six, Interprocessor Communication or IPC.

Before we get started, let's review the basic architecture of the F28M35x. Recall that this is the first device in the Concerto family. This device consists of two subsystems.

The first one is based on the ARM Cortex-M3, which controls the master subsystem. The master subsystem has a number of communication peripherals. The control subsystem is based on the TI C28x floating-point unit.

This subsystem has a number of real-time control peripherals, such as EPWM, ECAP, and EQEP. This session will concentrate on the mechanisms that the two subsystems can use to share information. This topic is divided into two parts.

Part a concentrates on the IPC device features. This includes shared RAM, message RAM, IPC registers, IPC interrupts and flags, and serial communication loopback. A second presentation will go into the IP software options.

So let's get started with the IPC device features. There are up to eight blocks of shared SARAM on a F28M35x device. These shared SARAM blocks are typically used by an application that can also be used for transferring messages and data. Each block can be individually owned by either the master subsystem or the control subsystem.

At reset, the master subsystem owns all of the shared SARAM blocks. In this configuration, the master subsystem can freely use the memory blocks. The M3 can read, write, or execute from the block. And the micro DMA can read or write.

On the control subsystem, the C28x and the C28x DMA can only read from these blocks. Blocks owned by the master subsystem can be used by the M3 to send messages to the C28. We refer to this as MtoC or master to control.

After reset, the M3 application can assign ownerships of blocks to the control subsystem. In this configuration, the control subsystem can freely use the block. The C28x can read, write, or execute from the block. But the master subsystem can only read from the block.

Blocks owned by the control subsystem can be used to send messages from the C28 to the M3. We'll refer to this as CtoM or control to master. For safety, shared memories can be further configured to disable master DMA right and/or CPU right and/or CPU execution.

The F28M35x has two dedicated message RAM blocks. Each block is 2 kilobytes in length. Unlike the shared SARAM blocks, these blocks provide communication in one direction only and cannot be reconfigured.

The first message SARAM is the master to control or MtoC. This block can be read or written to by the M3 and read by the C28. The M3 can write a message to this block. And then the C28 can read it.

The second message SARAM is the control to master or CtoM. This block can be read or written to by the C28 and read by the M3. This means the C28 can write a message to this block, and then the M3 can read it. After the sending CPU writes a message, it can inform the receiving CPU that it's available through an interrupt or flag. This will be discussed in detail later in this presentation.

The next silicon feature is the IPC message registers. These registers provide a very simple and flexible messaging scheme. It can be used like a mailbox to send messages back and forth.

These are dedicated registers that are mapped to both CPUs. We have named them IPCCOMMAND, IPCADDRESS, IPCDATAWRITE, and IPCDATAREAD. The actual definition of what the register contents means is actually up to the application software. TI's IPC-Lite drivers use the IPC message registers. This software is described in the second part of this presentation.

When the sending CPU wishes to inform the receiver that a message is ready, it can make use of either an interrupt or a flag. Note that interrupts are not required. There are identical IPC interrupt and flag resources on both the master subsystem and the control subsystem.

Each of the interrupts has a dedicated vector within the PIE or the NVIC. In addition, there are 28 flags available to each of the subsystems. These flags can be used for messages that are not time critical. Or they can be used to send status back to the originating processor, for example, if a message was a success or message was not understood.

The flags and interrupts can be used however the application sees fit and are not tied to particular operation and hardware. The TI IPC drivers provide a couple of options that will be discussed in the second part of this presentation. The registers to control the IPC interrupts and flags are all 32 bit.

The low bits, 0 through 3, will force an interrupt along with a flag. The high bits, bits 4 through 31, force the flag only. The requesting or the sending processor uses the Set, Flag, and Clear registers.

The Set register is used to send an interrupt and set the flag. Likewise, it can be used only to send a flag if desired. The Flag register indicates whether the Set register has been used. It indicates a message is pending and has not yet been acknowledged by the receiver.

On the receiving side, the Status register always reflects the Flag register. The ACK register is the acknowledge, which is used by the receiving processor to acknowledge that a message was received. And it will clear the flag. These registers are described in more detail on the next slide.

Notice that we use register prefixes to indicate the direction of communication. For example, MtoC IPC SET would be master to control. Likewise, CtoM IPC set would be control to master.

One note on this slide, either the Clear or Acknowledge can be used to clear this Flag and Status bits. Normally, only Acknowledge is used by the receiving CPU. Clear, however, may be used by the originating CPU in the case of a timeout or if the sending processor does not need acknowledgement. Note, however, that clearing flags will not clear and interrupt itself. On the next slide, I'll show an example of the C28x sending a message to the M3 using these registers.

In this case, the C28x is the originator. And the M3 is the receiver. This assumes that the C28x has already written a message to either the shared message RAM or the IPC message registers if needed. It should be noted that the interrupt itself could be a message with no extra data required.

First, the C28 writes a 1 to a bit in the CtoM IPC Set register. This is bit 0 through 3. If instead no interrupt was desired, bits 4 through 31 could be used.

An interrupt is sent to the NVIC and the M3. At the same time, the corresponding bit in the Flag register and the Status register are both set. Remember that the Flag register is on the sending side. And the Status register is on the receive side. This indicates that a message is pending and has not been acknowledged by the receiver.

The M3 reads the message and does what is asked and then writes to the ACK bit to acknowledge. This will clear the flag and the status bits. Note that the sending CPU can also clear the bit if desired using the CLR register. This does not, however, clear the interrupt from the NVIC or the M3. It simply clears the flag.

For sending messages in the opposite direction from the M3 to the C28, an identical set of resources exists. The last IPC silicon feature is serial communication to perform IPC. There is a mode called the serial port loopback, which enables IPC through the peripherals.

Supported in this mode is the UART to SCI or a SSI to SPI. The master subsystem can enable or disable this capability. And it does not require an external connection between the peripherals.

One thing to notice is that the pins can also be seen on the GPIOs when in this mode, which may be useful for debug. The other option is to connect the SSI to the SPI. This is available on SSI3 and SPIA.

The following modes are supported, SSI3 to SPIA where SPIA is the slave or where SPIA is the master. This concludes the silicon features for the interprocessor communication on the Concerto device. Please look for the second part of this presentation where Chrissy Chang will go through the TI software solutions for IPC.