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Hello and welcome to the TI Precision Lab discussing Input Offset Voltage (Vos) and Input Bias Current (Ib). In this video, we'll discuss op amp Vos specifications and Vos drift over temperature, as well as input bias current specifications and input bias current drift over temperature. We'll also show the range of Vos and Ib across many different TI op amps.

Let's start by defining offset voltage. Offset voltage is the differential input voltage that would have to be applied to force the op amps output to zero volts. Typical offset voltages range from millivolts down to microvolts, depending on the op amp model. Offset can be modeled as an internal DC source connected to the input of the op amp. Changing power supply voltage and common mode voltage will affect input offset voltage.

Looking at the inside of an op amp, we can see that the mismatch of transistors Q1 and Q2 in the differential input pair is what causes the offset voltage. In some cases, internal resistors ROS1 and ROS2 are laser trimmed in order to compensate for this mismatch and obtain very low offset voltage. In other cases, an internal digital correction circuit is used to minimize offset voltage and offset drift.

This slide introduces op amp specifications for offset. The top of the specification table is the test conditions for all the parameters in the data sheet. In this example, the temperature is 25 degrees Celsius, the load resistance is 10 kilo ohms, the load is connected to mid supply, and the common mode voltage is set to mid supply. These conditions are true unless otherwise specified.

If you look at the offset voltage specs, it lists some additional conditions. The supply voltage is plus or minus 15 volts, and the common mode voltage is zero volts. Also note that we have a typical and a maximum specification. The value listed in the typical specification will cover plus or minus one standard deviation R plus or minus sigma on a Gaussian distribution. This means that 68% of the device population will be less than the typical value. So in this case, 68% of the devices would have less than plus or minus 75 microvolts of Vos.

The maximum is a tested value, and so you will never find a device with greater than the maximum Vos of plus or minus 150 microvolts. We also have a Vos drift specification that is measured in microvolts per degrees C, describing how the Vos changes with temperature. In this case, the typical drift is given as 0.1 microvolts per degrees C.

The maximum drift is given as two microvolts per degrees C. Most op amp SPICE models include the effects of offset voltage. Several external conditions, such as power supply voltage and common mode voltage, affect the offset voltage on a real world device. These effects are also included in the simulation model. In order for the simulation result to match the offset specifications in the data sheet table, the same test conditions must be applied to the amplifier.

In this example, the power supply is set to five volts, the common mode voltage is set to mid supply R 2.5 volts, and the load is connected to mid supply in order to match the data sheet conditions. The typical offset specification is 150 microvolts, and the simulated offset is also 150 microvolts. The goal of our models is to target typical op amp performance.

The slope on offset voltage drift can be either positive or negative. This formula shows one possible definition for offset drift. This formula will produce a positive or a negative drift, depending on the slope of the curve. Some other definitions use the absolute value, so you will not have a negative offset.

This is the more common definition for drift which is separated into two different regions, although more than two regions could be used, if desired. The idea with this definition is that you get a more realistic view of what the expected error would be than if you only considered the endpoints over the entire region. In this example, you can see that the slope of the two separate regions is much more severe than the drift of the entire range. Note that the absolute value is used in the formula, so this formula will never give a negative result.

In this application example, we will see how to calculate the output voltage error from the offset voltage. Consider offset voltage as a DC voltage source in series with the non-inverting input of the op amp. We have a 0.1 millivolt, or 100 microvolt offset, in this case. The signal source is a very small input of 1 millivolt, so the offset will generate a fairly significant error.

The gain for this part is configured as 100 volts per volt, which can be calculated as R2 over R1 plus 1. The total output voltage is the series combination of the offset and the input signal are 1 millivolt plus 0.1 millivolts multiplied by the gain of 100, which gives us 110 millivolts. The offset accounts for about 10% error.

Offset drift calculations can be done in a similar manner. Notice that we have two sources, one for the initial offset, and one for the offset drift. The offset drift source will be zero at 25 degrees C. As the temperature deviates from 25 degrees C, the temperature difference will be multiplied by the offset drift to generate the additional offset voltage.

For example, at 25 degrees C we have 100 microvolts of offset, which is just the room temperature offset and no drift term. At 125 degrees C, we have a total of 250 microvolts. That is 100 microvolts from the initial offset, and 150 microvolts from the drift term.

The table on the right illustrates how the offset changes over temperature. Keep in mind that the slope of the offset drift can be either positive or negative, so both cases are shown. Drift is especially important in calibrated systems. In calibrated systems, room temperature offset is frequently measured and corrected for in software. Temperature drift, however, is often difficult and expensive to calibrate out, so devices with minimal drift are preferable.

This chart shows a range of offset voltages, from microvolt to millivolts, for different types of TI amplifiers. The first amplifier in the list, the OPA333, includes a Zero Drift apology which uses an internal digital calibration circuit to minimize offset and offset drift. Some precision bipolar amplifiers use laser trimming to minimize offset.

Often you must trade off bandwidth or other characteristics for low offset. For example, the OPA835 is optimized for speed, not for offset. Also commodity or low cost amplifiers are usually not optimized for low offset or low offset drift.

Let's now move on to input bias current, or Ib, and input bias current drift. Input bias current is the current flowing into the inputs of an op amp. These currents can be modeled as a current source connected to each input as shown in this figure. Ideally, the two input bias currents would be equal to each other and would cancel. In reality though, they are not equal, and the difference of these currents is defined as input offset current. If the input offset current is low, it's possible to match the impedances connected to each input and cancel the offset developed from the input bias currents.

In a bipolar amplifier, input bias current is the current flowing into the base of each transistor in the input pair. Generally, the bias current for bipolar amplifiers is larger than the bias current for MOSFET and JFET amplifiers. Typical numbers are in the range of nanoamps. You can see in the case of the LM741C, the input offset current is about 200 nanoamps max, and the input bias current is about 500 nanoamps max.

Some precision bipolar op amps use a method called bias current cancellation in order to minimize bias current. This is done inside the op amp, so no external components are required. The amplifier simply behaves like a bipolar amplifier with very low bias current. Bias current cancellation is done by measuring the input bias current, and summing in equal but opposite currents, which cancel the bias current. This effectively takes an amplifier with hundreds of nanoamps of bias current down to single nanoamps of bias current.

You can see from the specification table in this example that the input bias current of the OPA277 is plus or minus one nanoamp maximum. In the previous example, the bias current had to flow into the base of a transistor, so the bias current could only have one polarity. In this case, however, the bias current can have either polarity, since the bias current cancellation circuit is not perfect, and it's not known whether the polarity of the residual current will be positive or negative.

In the case of MOSFET or JFET op amps, the input bias current is primarily due to the leakage of the input ESD protection diodes. The gate of the input MOSFET transistors has extremely low leakage, so it doesn't contribute significant bias current. You can see in this example that the OPA369 has 50 picoamps max of input bias current.

One thing to remember with low bias current amplifiers is the effect of Ib over temperature. In MOSFET amplifiers, the bias current can double every 10 degrees C. You can see in the example on the left, with the OPA350, that the input bias current increases significantly at temperatures above 25 degrees C. If you only considered the room temperature value of Ib, and then operated the amplifier at elevated temperature, you would have significant errors. Notice that the vertical axis of the plot uses a logarithmic scale.

With a bipolar amplifier, the initial input bias current at room temperature is often large enough such that the relative change in input bias current over temperature is minimized. You can see in the example on the right with the OPA277 that the input bias current starts to increase at temperatures above 75 degrees C. Note, however, that the vertical axis uses a linear scale.

This bias current calculation is very similar to what was done for offset voltage. First, we model the bias currents as two current sources connected to the op amp inputs. Note that the input bias current connected to the non-inverting input is flowing back into the input signal source. And since there is no source resistance, that bias current source does not add any error voltage. If there was a source resistance connected to the non-inverting input, the bias current would generate an error voltage.

The error in this configuration arises entirely from the input bias current source on the inverting input, which flows into the feedback network of R1 and R2. If we perform a nodal analysis, we can see that the output voltage caused by Ib is equal to Ib multiplied by Rf. We can then calculate the output caused by Ib and the output from the input signal. Using superposition, we can add the output signal from the bias current equal to 20 millivolts and the output signal from the input source equal to 100 millivolts, since they are independent.

In this example, the total output voltage equals 120 millivolts, and the error introduced by the input bias current is about 20%. Please keep in mind that this was an error calculation using high temperature Ib values. If this calculation was done at room temperature, the error would have been significantly smaller.

This table gives a range of input bias currents for different TI op amps. Values can range from FEM to amps for specialized CMOS amplifiers all the way up to hundreds of nanoamps for high speed and commodity op amps. Note that bipolar amplifiers will always have higher input bias currents than CMOS amplifiers. Also, bipolar amplifiers with bias current cancellation circuitry, such as the OPA277, will have lower input bias current than bipolar op amps without cancellation, such as the OPA211.

That concludes this video. Thank you for watching. Please try the quiz to check your understanding of this video's content.

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