Welcome to the MSP432 MCUs Training. It is part 2, and we will look into the Cortex-M4F Core. The MSP432 uses a 32-bit Cortex-M4F CPU. The CPU has 32-bit data path, 32-bit register bank, and 32-bit memory interfaces. The CPU uses a Harvard architecture, which means that it has a separate instruction bus and data bus. This allows the instructions and data accesses to take place at the same time. And as a result of this, the performance of the processor increases because the data accesses do not affect, or interfere with, the instruction pipeline.

This feature results in multiple buses and interfaces across the Cortex-M4F, each with optimized usage and the ability to be used simultaneously. However, the instruction and data buses share the same memory space, and that is called a unified memory system.

So in this particular Cortex-M4F flavor that was chosen by MSP432, the device also includes a Nested Vectored Interrupt Controller, or short NVIC. It also includes a FPU, a Floating-Point Unit, as well as the enhanced DSP instruction set that comes with Cortex-M4.

From the debugger standpoint, it features a standardized Cortex-M Debugger Module, a Serial Wire Debug, as well as ITM Trace support. Since there is a Cortex-M4F core, it also inherits a number of peripherals that come from a Cortex [INAUDIBLE] family, including the micro DMA, SysTick, as well as Interrupt, as mentioned before.

This slide gives you a quick overview to compare the different flavors of the Cortex-M cores, starting with Cortex-M0 all the way to Cortex-M4. As you can see, as we increase the complexity in the core, more instructions are being added to the instruction set, as well as other additional features like hardware multiplier, hardware divider, saturated math capabilities, DSP construction extensions, as well as a fl Unit. You might also notice that moving from Cortex-M0 and M0+, to Cortex-M3 and M4, the ARM architecture also changes from Von Neumann to Harvard, which adds an additional data bus in addition to the instruction bus. The reason why Cortex-M4F was chosen for MSP432 is because it provides the most performance and capabilities, while adding minimal additional power consumption. This will be shown in the next slide showing the result of Cortex-M4F being using in MSP432.

Lastly, the Floating-Point Unit is another addition to the Cortex-M4F version chosen by the MSP432 family. The Cortex-M4F FPU fully supports single-precision addition, subtraction, multiplication, divide, and square root, so on, so forth. One thing to note is that FPU support is already enabled automatically in most of the compilers, so without a single click, you can already use Floating-Point operations in your application with MSP432.

Since MSP432 uses are standardized core, it would be good to measure its performance in a standardized way. CoreMark is a standardized benchmark that is used to measure the performance of the processor core. The CoreMark developed by the Embedded Microprocessor Benchmark Consortium, or EEMBC, to help system designers select the most optimal processors, and understand the performance and energy characteristics of the systems.

MSP432 essentially scores the highest possible score achievable on a Cortex-M4F platform. We know that that is the highest score, because it is also the score that an ideal Cortex-M4F core implementation can achieve. This is the same information that is shown on the Cortex-M4 page on the [INAUDIBLE] website.

In addition to CoreMark, EEMBC also develop another benchmark that measures the energy efficiency of ultra-low-power microcontrollers. ULPBench will include a set of tests that measure the device energy consumption when performing a predefined task that is applicable to an ultra-low-power application.

So ULPBench was officially released in the late 2014, and since then, has become a standard low-energy benchmark for the wide range of microcontrollers in the industry.

So the benchmark is measured as follows. Usually a task involves a microcontroller to wake up once per second, to execute a predefined workload. Once it is completed, the microcontroller needs to go back to sleep, and then wake up again one second later. And the overall energy consumed by the entire system to accomplish the task is measured over this one-second period. As a result, the lower the energy consumed, the better you are as a microcontroller and as system.

So to make the score a little more intuitive for the readers, the score is actually calculated by using 1000, and then divided by the total energy consumption measured in microjoules. As you can see, the result is actually quite impressive for MSP devices. From the graph, the MSP432 achieved the highest ULPBench score in the world today at 153.3.

It is better than competition ranging from Cortex-M4, Cortex-M3, all the way down to Cortex-M0+, as well as other proprietary architectures. This goes to show that performance does not always require more power. And when implemented correctly, a high-performance core such as the Cortex-M4F on MSP432 can still yield lower power than other simplified core.

So this concludes the Part 2 of the MSP432 training series. In the next parts of the training series, we will uncover what was done to the design of the device, the power system, the clocking structure, the intelligent peripherals, the software tools, debuggers, all were developed to help us achieving this world's lowest energy microcontroller for Cortex-M4, and achieved the highest score on ULPBench. Thanks for watching.