Hi, I'm Peggy Liska with the C2000 digital power team. I want to go through, today, the topic of designing and implementing digital power controllers on the C2000 microcontroller family. The three topics we'll cover include a design example based around closed loop control, implementing that control law on the C2000 processor, and then some follow-up design resources that you can reference to get your design going on the C2000 devices.

First off, I want to address a few of the digital power design challenges that you might face when designing a digital power compensator. The first is actually converting from the analog domain to the digital domain. The types of issues you might run into include limit cycle issues, control loop latency, and some control law coding implementation artifacts.

We'll go through some ways that you can tune the loop using software and how you can implement the final control law in a C2000 microcontroller. Let's start with the first section, and walk through a design example. First, it's important to know what type of requirements to have on your digital controller in order to implement a digital control loop.

The first of these is a high speed ADC, or analog to digital converter, that can be synchronized with the switching patterns of the PWM module or pulse width modulation module. The second characteristic that you need on your processor is a high performance CPU that allows for low latency computation of the control law math.

The third component is a flexible PWM generator that can do various high frequency output configurations to control different power topologies. And the fourth component is a high speed comparator subsystem that allows you to trip the PWM on any type of over current, under current, over-voltage type situation in your system. This needs to be closely coupled with the PWM module to allow for the lowest possible latency of a trip event when it occurs.

So let's move into how you would generate the control law code that would run on the main CPU that we show in the previous slide. Typically, analog control systems are very well understood. And the theory is very practical, and well thought out, and well taught. The plant and feedback subsystems can be modeled using Laplace transforms.

And the compensator is then designed to meet those frequency and transient response requirements of the output. In the digital domain, we add two components. First, a hold. So this would be the PWM module that's generating the signals that would then be output on the plant, which you see here as g of s and the sampler, which is our analog to digital converter, or A-to-D, that we have on chip to measure in signals from the plant, and convert them into digital values that we can use in the discrete time domain you see on the left hand side of the screen.

Since this is a discrete time representation, we want to be sure that we use the z transform rather than a Laplace transform as you can see designated by the f of z on the left hand side of the discrete time graph. A linear time system can be represented using this transfer function shown at the top of the screen. This same transfer function can be transformed into the z domain and given the form is shown halfway down the screen.

The relationship between a z and s to make the conversions from the Laplace domain to the z domain are shown on the bottom half of the slide. You can see that the bottom equation where s is approximately equivalent to the equation shown on the right hand side. You can see how the z transform values are converted back to the s domain.

This is an approximation known as the Tustin transformation and gives you a very close representation of the equation z equals e to the st. The frequency response of a system is typically measured and displayed on a Bode plot so that you can analyze various characteristics of the system.

In a digital system, you can see that only the frequencies below the Nyquist frequency shown as omega n here in the graph are plotted. This is because after this point, you have sampling artifacts that prevents you from having a one to one mapping from the continuous time domain to the discrete time domain. You'll also notice the greater phase lag in the discrete time system.

This has to do with the measuring of our ADC, and the output of our PWM, and the delay between the two. This introduces a phase lag into the system that is not characteristic of analog control systems but is present in digital control systems. So let's move into the design sample itself.

The diagram here shows a buck converter. And the value shown on the right hand side come from one of TI's evaluation modules for a buck converter. So these values are real values that have been tested and implemented in a design that we created.

The switching frequency of the design is one megahertz. And if you wanted to calculate the transfer function for the buck output power stage shown here, you would use the equation shown halfway down the slide. G of s equals the large equation shown. As you can see, the constants for the inductor, capacitor, and resistor values can be input into this equation to generate the equation at the bottom of the slide.

This is the transfer function for the buck power stage plant. When plotted in a Bode plot example, you can see that there is, both, a gain plot shown on the top half of the slide, and a phase plot shown on the bottom half of the slide. The gain plot has a double pole on the output and you can see the LC filter.

This creates a bump in the top part or the gain plot of the graph. You can also see that there is actually some phase lead on the bottom graph that is created from the zero of the ESR. So there are both poles and zeroes present in this plant and the characteristics of which you can see implemented here in the gain and phase plots.

We now need to design a compensator in order to control this plant. So in this case, we've shown an analog compensator. Typically, when you want to design a digital compensator, you start first with the analog domain. And then, transform it into the digital domain.

So we'll start with the analog compensator shown here. This is a type 3 classical compensator. And the equation for the transfer function is shown on the slide. This can be rewritten as the equation on the bottom of the slide to easily denote the frequency location of the poles and zeroes, which you can see designated in the final location on the slide.

This is the frequency plot of the open loop with the analog compensator. It shows that we placed a complex zero pair on the bump shown on the plant graph to cancel out the complex poll pair that was present in the buck power stage. The integrator on the left hand side allows you to have a 20 dB per decade roll off, as well as zero steady state error.

You can see that the high frequency poles located in the compensator are out to the right as far as higher frequencies are concerned. This allows you to move the phase lead that we initially saw in the plant over to a point lower you can see in the phase graph. This will give you the desired phase margin and gain margin that you're looking for in the open loop of the plant and compensator.

We now want to transform our compensator into the discrete time domain. We do this by taking the final form of the equation from the analog compensator and substitute in the text in approximation values for all instances of s. An important step after making this substitution is to be sure that the 0 Hertz games of the transfer functions are matched.

This can be done by setting each equation, both, the f of s and f of z to 0, and solving to determine the value of the offset between the two. The equation shown at the bottom of the slide is what is typically shown for a digital compensator in the third order like we saw originally from the type 3 in the analog domain.

You see that there are seven coefficients. b0, b1, b2, b3, and a1, a2, and a3. These are what change in a digital compensator. And we'll look into how these values affect the overall compensator itself later on.

As you can see in this plot, we have both the analog and the digital domain values plotted to see the difference and compare how closely the approximation allows us to transform from the analog domain to the digital domain. As you can see, it very closely matches up until the Nyquist frequency. And at that point, you can see that the phase plot diverges as expected with a phase lag. And the gain plot does ultrasound as well.

We now need to take the equation for the digital compensator and convert it into a difference equation. This gets us a step closer to putting it into a format that can be coded into the microcontroller. What we do first is normalize the bottom portion of the equation so that the first coefficient is 1. This is already performed on the previous slide.

So now if we cross multiply the two, we're able to set the equation equal to the output u of z in terms of the input, e of z. We then apply a shifting property of the z transform that allows us to take any variable of z to a negative power and convert it to a sampling value. K minus 1, for instance, corresponds to z to the negative. 1.

This means that k is our current sample value. k minus 1 is our previous sample. k minus 2 was the sample before that. And k minus 3 was the sample before that one. So this allows us to have the equation written in terms of sample values.

Let's go through some limitations that occur when you try to put this equation into a processor. The first of which talks about the resolution of your analog to digital converter versus the resolution of your PWM output.

The delta b shown in the graph is the amount of change from your analog to digital converter. This means there is this many number of steps shown in the graph that the ADC can accurately measure. So in other words, the closer the lines are together, the higher the resolution.

Delta u shows the resolution capabilities of the PWM module. As shown in the first graph, if you have a higher resolution ADC than you do a high resolution output, then you see oscillations on the output voltage. This is due to the fact that the ADC is capable of measuring more closely what the output voltage is than the PWM is able to actually regulate that output voltage.

In this example shown on the right, you can see that the delta b, the change between the ADC resolution, is less than delta u, which means that the PWM frequency resolution is actually higher. This allows you to have a more stable output because as the ADC measures the change in the output voltage, the PWM can more finely tune and control the output on the PWM stage and, therefore, on the power stage controlling the output.

High resolution PWM is a feature that's implemented on the C2000 microcontrollers. It takes a single time period shown here as TB clock, and divides that into a high resolution clock of many more switching patterns. In the case of the C2000, you have an accuracy of approximately 150 picoseconds, which allows you to more finally control the edge of the PWM output.

And therefore, you have higher resolution on your output compared to the resolution of the ADC on the input. This slide shows how the output actually changes on a power supply system shown in the top half of the screen by measuring the oscilloscope output shown in the bottom half of the screen. You can see on the left hand side that there is an output with only 10 nanoseconds of edge resolution. And the jitter on the output is quite significant.

But with the high resolution PWM shown on the right hand side, 150 picoseconds, you can see that jitter is removed, and the oscillations are steadied out in the final output of the power stage. Section two will go through implementing the control law that we calculated previously in the design example and getting it into a microcontroller so that it can be processed as control algorithms.

There are several typical, common controller types. They are listed on the left hand side of the screen. And the known transfer function for the use is listed, as well. This is then converted to the control law equivalent in the digital domain. You'll notice that there's quite a bit of similarities between the control law functions on the digital domain, regardless of the type of controller that's used.

This means that in the digital domain, there's very little modifications needed in the code in order to switch between the different types of controllers shown on the left hand side. The major change between these functions are the coefficients that we stated earlier. b0, 1, 2, and 3, and a1, 2, and 3.

Here's an example for how you would create the equation that we showed earlier where u of k, the output, is equal to a coefficient times the input of multiple time delayed terms in a system. So the final equation is shown at the bottom of the slide in the yellow box. Taking this equation, we can actually represent it using a state or block diagram shown here.

Across the top of the diagram, you see a time delay of 1 to result in e of k minus 1, another time delay to result in ek minus 2, and a third time delay to show a result of e of k minus 3. Each of these samples or delayed samples are then multiplied and added together to equate to the output shown in the equation.

This diagram can then be rewritten in a digital form as an array. The output at element 0 is equal to the coefficient b0 times the element in array e at 0.0. You can see how this would go through and give you the equation shown at the bottom of the graph using two arrays in code. Array u and array e.

Let's walk through how we might manipulate these arrays in our code. Here's how you would program into a microcontroller. We have the seven coefficients that I mentioned earlier. a1, 2, and 3, and b0, 1, 2, and 3. A constant value, as well as a variable or a value for defining the PWM duty cycle address.

We then have several variables in the code that we can use to set various parameters, such as the reference input voltage, what was measured back as the ADC feedback, and the two arrays that we saw earlier, each three elements long. The final equation that you see is a type 3 control law calculation.

We first measure the error between was referenced as the desired input and the measured value of the ADC. This is stored in the input array of e. We then calculate the first element or element 0 in the output array u. This is done using the equation we saw earlier.

And all we do at this point is shift the values in the array such that there is now an empty space at the beginning of both arrays in element 0. At this point, we then output the duty cycle on the PWM and allow the power stage to be controlled using the output of our control law calculation.

Let's talk about the importance of control loop delay. The diagram here shows how you would typically process through a system. The first point, the blue triangle shows a sample point on the ADC. This is the point at which you've measured in the value of the output, and you need to compute how to control law change the output using the PWM.

The time in a before you get to the interrupt shows what it might take in a processor to convert that analog value to a digital measurement. The delay between the interrupt and the ISR beginning could be due to some code in the system that is noninterruptable or some other delay in the processor itself.

Section B shows the actual interrupt service routine or ISR code that's calculated. First, you have to context save the processor. Read the ADC. Calculate the new control code using the function we described earlier. Update the controller or, in this case, our PWM.

Do some supervisory tasks, such as communicating or doing a watchdog, work reset or timer, check or something to that effect. Acknowledge the interrupt. And do a context restore. At this point, the ISRNs and you wait until the next sample point. As we said, the update controller portion or where we change our PWM happens about part way through ISR.

This point compared to the initial sample point is our control loop delay. In a digital system, this is what's causing the phase lag and any other delays in your system. You've sampled and read using the ADC. But you have a delay before which you can make an impact or a change on the output.

This needs to be reduced as much as possible to allow your system to be as fast and low latency as possible. There are several ways we can do this. Let's look at one attempt. Pre-computation allows you to take the portion that you don't know at your current sample time, and the values that you do know prior to taking that sample, and pre-compute the values you know, and only wait to calculate the values that you don't know.

In other words, this is what it looks like in C code. So if we look at the control law function, we can see that we, again, measure what our reference point should be and what we're actually getting on the ADC, store that as our error, calculate the new value in our output of u 0, and then output to the PWM.

The variable v was stored previously using the pre-computation equation shown next. You can see that then we shift our variables in the array, and wait for the next time the function is called. This example shows you how we've reduced the delay between reading in on the ADC and outputting on the PWM.

Typical control software structure consists of a main loop within which a while loop is inserted. And an interrupt will interrupt the while loop at any given time. The code we've been looking at exists in the interrupt ISR shown on the right hand side.

The C2000 microcontrollers are supported by a digital power library, which we can represent using this module diagram shown here. The yellow blocks represent functions in the library that are purely computational, such as our control our computations. The blue blocks show any type of function that interacts with the module or a pen.

So the PWM shows how we can take a variable-- in this case, duty variable-- and output that on our PWM 1a channel. Similarly, we can read in, a value on ADC channel 1, and store that into variable V out. The way that we get these variables in and out of the various functions is with the use of pointers, which you can see on the right hand side.

The various pointers are set to values. Vref, Vout, and duty. And these are then assigned to the inputs and outputs of the various functions. This modular architecture for the software allows us to do different things. First off, we can control multiple power stages. So you can replicate the number of blocks that you want to use, change out the type of controller, perhaps, or which PWM and ADC channels you're interfacing with.

You can also implement and interrupt service routine structure with a lower latency background task. This allows you to do something that's less time critical in the background, and execute your interrupt service routine in a very time critical, low latency fashion.

There are also additional ways you can configure your software to make it more useful in your end system. This is one example that shows possibly using various coefficients shown in the blue box in the bottom left, having a startup sequence as shown in the yellow box on the left hand side, and being able to switch in and out the control, at some point, to control an output power stage.

On the C2000 microcontroller family, the control accelerator or CLA is an independent, 32-bit floating point core. This runs in parallel with the main CPU and runs completely standalone. This allows you to run your control loop code entirely on the CLA without interrupting or interacting with the CPU.

So to show this on the diagram that we looked at earlier, you can see there are several benefits to running code on a CLA. First of all, the interrupt latency or jitter that you might encounter by a noninterruptible code piece or something else in the processor is completely eliminated because the CLA runs single task entirely through to completion.

There's no need for a context save or context restore. The CLA is also very highly optimized for control loop computations. Therefore, we can reduce the overall control loop delay by more quickly and efficiently computing the control law code.

The CPU is left entirely free to do other computations in the code. The CLA is entirely handling the control law, the reading of the ADC, and the output on the PWM. This shows an example of how you would write code for the CLA. You can see that it looks very similar to the code that we had earlier.

But the way that we set this up is in the task format. The CLA itself has 8 tasks. Typically, the last task is reserved to do initialization of the CLA. And the other tasks are used at various points in the program, depending on what you want the CLA to execute and when.

So as you can see, we read a and r feedback variable from our ADC, feed those two values, the reference and what was measured as the feedback, into our 2 pole 2 0 controller, run our control law code, and calculate a new duty that is then written to the PWM channel.

We'll now move into the final section of the training where we'll go through some development tools and design resources that you can use when developing a digital power compensator and control loop on a C2000 microcontroller. We have several reference designs that are specifically targeted at applications that commonly use or could benefit from digital control.

The first of these is a two phase, interleaved boost, power factor correction board. The diagram in the top right shows you a PFC power stage. The green tags represents points at which you want to make measurements with the ADC. And the red tags indicate points at which you would control a FET with a PWM output.

These are then tied to a C2000 microcontroller that has on chip ADC, PWM, and CPU. This board is our half bridge resident LLC kit. Similarly, you can see in the diagram how you would configure the PWMs and the ADCs to connect to this power stage. The two FETs on the right hand side are for synchronous rectification, which can be an optional feature for this topology.

As you can see in the picture on the bottom left, there is a card slot for you to enter any C2000 controller that you would like to evaluate to control this power stage. As you'll see on the next slide, this board has been populated with one version of our control card. You can take this and use it to test out various controllers in the C2000 family.

This is our phase shifted full bridge kit. The block diagram of which is in the right hand corner. And again, you can see the synchronous rectification FETs on the right hand side of the diagram and the full bridge on the left hand side. The dotted red line indicates isolation between the two because, typically, there is a high voltage bus and a low voltage DC bus inherent in this system.

We also have a solar micro inverter kit consisting of two components. The MPPT DC to DC power stage, maximum PowerPoint tracking, DC to DC stage, or the DCAC inverter stage. Both of these are combined together. They're on this single kit as shown in the diagram on the bottom to then be controlled by a single C2000 microcontroller.

We also have a bi-directional DC-DC converter board. This allows you to do bi-directional 400 volt to 12 volt DC-DC power. The final kit we want to showcase is our digital power booster pack. This is a buck converter that converts 9 volts down to 2 bolts. The purpose of this board is to explore the software architecture on the C2000 microcontrollers, as well as our power suite digital power software tools.

Power suite is a combination of three tools. The compensation designer, SFRA or software frequency response analyzer, and solution adapter. These three tools combine together to allow you to design a digital power system basing it TI's code example structure and modifying it using a GUI for your own personal code power stage structure.

You start with a solution adapter. And this allows you to change which pins on the C2000 are connected to which points in your power stage. And then, the values of the power stage are input into the bottom half of the GUI. You then take that power stage that you've designed in the GUI and on your board, feed those values into the compensation designer tool, which allows you to place the poles and zeroes of your compensator accordingly so that you can compensate for the power stage that is being modeled in the compensation designer itself.

The code that will be created will then be downloaded into the processor, the microcontroller, run on the power stage, and at that point, you can actually measure the effectiveness of your controller, your compensator, using our software frequency response analyzer. This gives you the closed loop performance by measuring the open loop gain in the plant [INAUDIBLE] see response.

This is then plotted. And the values from the SFRA for the plant can be fed back into the compensation designer to be used as the true plant measured values versus the modeled values that were originally used. And you can then recalculate and replace the poles and zeroes as necessary to tune your digital power compensator.

This is a little bit of the theory behind how the frequency response analyzer works. You take the plant, the control on the feedback shown here, and at the point where you began to compute the control law, you inject a sine wave frequency. This is then propagated through the control loop and measured at various points.

The amplitude of this fixed function sine wave is then measured. And the phase of the plot can be determined. You iterate through and step through various frequencies on that sine wave to then create the Bode plots for, both, the gain and the phase plots of your Bode graph. As shown here, you Can see that we would measure, in this case, the plant and plot those points accordingly.

Some benefits of using a software frequency response analyzer are that you can do, entirely in software, the system frequency response measurement. This prevents you from having to cut the control loop and insert a probe or some other measurement device. It allows you to design the compensator, and measure the stability response of the system.

You can use this periodically in your system to measure the health of your power stage. So in this case, you could measure the gain and phase margins of your design and monitor those over time to track and see if they are getting to a point where the control loop might become unstable. Here's a picture of the compensation designer. And it shows you how you can place the frequency of the poles and zeroes.

The poles are designated as X's on the graph. And the zeroes are designated as red dots. The frequency of which is changed by inputting a value into the text box in the upper portion of the GUI. And the seven coefficients that we talked about in the control are calculated and automatically copied into the code to allow you to compile and run the new control law on your microcontroller.

This training has, hopefully, covered the main points that we discussed at the beginning. We talked through how to design a compensator in the digital domain, the limit cycle issues that you might run into, the importance of control law latency and reducing the control law latency, how to implement control law in code, adapting that code for a specific device, and tuning a loop using our power suite to software tools.

For more information, you can check out any of the training shown here on the slide. Thank you for your time.