Understanding Clock Jitter Impact to ADC SNR
00:02:56
|
05 AUG 2015
This video discusses the sampling clock phase noise performance and how its performance over frequency offset impacts the GSPS ADC SNR performance.
Resources
This video is part of a series
-
High-speed signal chain training series
video-playlist (18 videos) -
High-speed signal chain training series
video-playlist (17 videos)