Choosing the Best ADC Architecture: Part 2 – The successive approximation register ADC
This video provides an overview of how a SAR ADC works. SAR ADCs provide a good trade-off between speed, resolution and power. This video walks through the typical topology of a SAR ADC, conversion process, acquisition phase, and more.
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Hello. My name is Luis Chioye. I am an applications engineer with Texas Instruments' Precision Data Converter team.
And I'm Anthony Vaughan with TI's Precision Analog Marketing team. Today we're going to give you an overview on how a Successive Approximation Register, or SAR ADC works.
The typical topology of a Successive Approximation ADC consists of a sample and [INAUDIBLE] structure, an analog comparator, a successive approximation register, and N-bit search digital to analog converter, or DAC. A typical SAR conversion cycle consist of two phases-- a sampling phase, or acquisition period, and a conversion phase.
The accuracy of the conversion result is dependent on several factors. From the extrinsic point of view, the quality of the source signal and SAR driving circuitry play a significant role as well as the accuracy and instability of the reference voltage. From the ADC intrinsic point of view, the performance of the device is dependent on the accuracy of the internal DAC and comparator.
The conversion process starts with the acquisition phase, or sampling period. During the sampling period, switch S2 is open and switch S1 closes, and the analog input signal is allowed to charge the ADC sample and hold capacitor, or CSH, to the voltage level of the analog input. The voltage across the sampling capacitor charges with a single pole response.
During the acquisition time, the voltage on the sampling capacitor needs to charge from an initial voltage, VSH0, to the final target input signal level of VN. By the end of the acquisition time, prior to the conversion phase, the voltage in the sample capacitor must be settled to the required resolution, and the voltage difference between the sampling capacitor and input voltage should be less than half of an LSB.
This is a fundamental requirement to obtain accurate conversion results. If you consider the ADC sample and hold structure exclusively, this settling time depends on the internal sampling capacitor and the switch resistance, RS1. From the time constant, t equals RS1 times CSH, we can derive the settling time of this single pole system. The minimum acquisition time for the SAR converter is the time required for the sampling mechanism to capture the input voltage and settle.
The required settling time for the ADC equivalent input network can be calculated with the above set of equations. In this first order system, the user needs to allow a minimum number of RC time constants for the input voltage to settle within half an LSB. For example, a 12 bit resolution ADC requires nine time constants to settle from an initial voltage of serial ports to the full scale within half an LSB.
Similarity, the certain requirements for a 16 bit resolution ADC will be more stringent, and the user will need to allow at least 12 time constants to ensure the sample and whole voltage settles within half an LSB. At the end of a decision phase, switch one opens, and the sample and hold is disconnected from the external circuit.
Switch S2 connects the sample capacitor to the internal comparator, and the conversion phase starts, where the sample voltage is compared against the output of the NP search stack. The NP search stack processes binary voided analog voltages proportional to the reference as each bit decision is made into the binary voided search.
The binary search starts with the most significant bit decision, and the tests are repeated for each binary voiced bit until the least significant bit decision is made. The value of each binary voided bit is based on whether the analog input voltage is higher or lower than the DAC voltage. The successive approximation register provides additional code to the internal DAC during each conversion clock cycle. The conversion time is a function of the conversion clock frequency and the resolution of the ADC.
In the simplified 5-bit [INAUDIBLE] ADC example of volt, five conversion clock cycles are required to reach the end of conversion. In most SAR ADC devices, after the device reaches the end conversion, the device returns to the acquisition mode.
Depending on the specific SAR ADC circuit, the initial voltage on the sample and hold capacitor during the next sampling phase may be reset to a mid point voltage, or it may keep a value on the last sample voltage. The device will trigger the next conversion after the next start conversion signal is received.
In summary, the SAR ADC is a very popular topology used in general purpose acquisition systems. They provide a good trade off between speed, resolution, and power. Data rates are available up to four mega samples per second, and resolutions up to 18 bits. A key advantage of the SAR ADC is the precise control of the point and time sampling, and virtually zero latency.
These characteristics may be beneficial in control systems and applications that require a fast response. For more information about precision ADCs, or to order a development kit, visit the TI precision ADC web page at ti.com/precisionadc. There are a number of resources available to help you evaluate and develop a system based on these ADCs. The TI Designs Precision page features several reference designs that can help speed the development of a system.
We hope you have found this overview useful. Thank you for watching.
This video is part of a series
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Choosing the best ADC architecture
video-playlist (4 videos)