Hello, and welcome to our in-depth look at interfacing to a precision DAC. In this video, we will go over the basics of SPI communication, and then go over examples with actual precision DAC devices.

The digital input to a DAC can be serial, where all the data bits are on a single physical line, or parallel, where there's one line for each bit of data. For precision DACs, serial is most commonly either SPI, three or four wire, or I2C, two wire.

The device on the top has a SPI interface. And in the middle is an I2C interface. We will touch on the former during this video.

Parallel has one data line per bit, plus other control and address lines. This device, for example, has 12 data bits plus 2 control lines for a total of 14 pins dedicated to the communication interface. It's clear that a parallel interface requires a much larger number of pins than serial. But the trade-off is the parallel can often have a much higher effective bit rate.

However, for precision DACs, the output settling time limits the speed advantage. Most modern DACs have a serial interface, most of which are SPI. And this will be the focus of this video.

Let's jump right into interfacing to a SPI device. There are two device rolls in SPI, the master and slave.

The master is the source of the device input data and is usually a microcontroller or DSP. The master controls the serial clock and chip select.

There can only be one master per bus. But multiple slaves can operate on the same bus. Each slave requires its own chip select line from the master.

SPI has two control lines, SCLK and chip select. And two data lines, serial data out and serial data in. SCLK is a square wave driven by the master that controls how fast data is sent and when that data is latched. Chip select is driven by the master. It activates the slave devices SPI bus so that the slave knows to listen for commands and data.

SDO and SDI are also called Master Out Slave In, and Master In Slave Out, respectively. They are uni-directional data lines, which each device places data on in sync with the clock pulses. The serial data out line of the master connects to the serial data in line of the slaves, and vice versa.

Data latching takes place on the critical edge of the SCLK. The edge refers to the point in time where the voltage level changes from low to high, which is called the rising edge, or from high to low, the falling edge. Either edge can be the critical edge depending on the device. And some devices use one edge to clock data in and the other edge to clock data out.

On the critical edge of each SCLK pulse, the device latches in the values seen on the data pin at the instant SCLK reaches the threshold voltage. This voltage is not a fixed number, and is different for the rising and falling edges.

Here we'll take a look at how data is clocked into a DAC. For a basic DAC, data only travels along the Master Out Slave In line, which is how the microcontroller or DSP transmits the digital input code to be converted. Chip select is active low, which means that when the master brings chip select to 0 volts, the SPI bus for the DAC becomes active.

To start the data transfer, the master brings chip select low and places data on the DAC serial data in. In this case, a one. The critical edge is the rising edge of SCLK. So the point at which the data is read by the DAC is indicated by the red line.

At the critical edge of the second clock pulse, the DAC reads the next bit set up by the master, which is a zero. The third bit is a one, as is the fourth, followed by 0, 0, 0, and finally a one. So the 8-bit input code sent to the DAC is 10110001.

To finish the data transfer, the master brings chip select back to its high state. In this example, the DAC has the full code latched into its registers after the eighth critical edge. But typically it does not update the input shift register until the chip select is brought high.

Data sheet timing diagrams and characteristics provide specific requirements for the SPI interface used to communicate with a device. Clock phase and polarity, setup and hold time, and the number of bits per exchange are critical. There may also be supplemental serial interface application sections for devices that have additional features or registers that can be accessed over the SPI bus.

The setup and hold time are two timing requirements that describe how data needs to be setup and held by the master device in relation to the critical edge. The setup time is the minimum for how long the data must be set at its desired value before the transition threshold of the critical edge. The hold time is the minimum for how long after the critical edge transition the data must stay at that value. Violating either of these parameters can result in the desired data not being clocked in.

Multiple DAC slaves that have SDO functionality can often be daisy-chained together to minimize the number of chip select lines required and simplify master programming. In this example with three slaves, the data for the furthest slave, D3, is clocked into the first slave. While chip select is still low, the next data packet, D2, is sent. And D3 is passed to the second slave via the first slave serial data out.

Once the data reaches the furthest slave, chip select is brought high. And each slave device has the data intended for it.

With all the knowledge we've gained on SPI communication, let's look at two examples of communication with a DAC over SPI. We will start with communication to DAC8811, a simple single channel multiplying DAC.

When the chip select line falls, communication is signalled to begin. With each subsequent rising edge of the clock, data is latched into the input buffer. As is common with most SPI interfaces, the first bit transferred on the data line is the most significant bit. Then the transfer works progressively down to the least significant bit.

DAC8811 is a 16-bit device. So after the 16th bit is transferred, bit zero, chip select returns to the high state to signal that communication has been completed.

The second example is with DAC8670, a current and voltage output DAC with more than one register to write to. DAC8760 is also 16-bit device. But unlike the previous example with DAC8811, the SPI communication transfers 24 bits instead of 16.

Since the DAC8760 has a number of different registers to write to, the SPI command has to identify an address to send the data word to. This address will point to one of the device registers to perform a specific function. For instance, if the address points to the DAC data register, the data word you send will consist of 16 bits of data that will appear on the DAC output.

If instead the address points to the configuration register, you can make changes to the current output range of the DAC, or enable and disable CRC. in the case of the addition of address bits, there's no real difference in how the physical communication is done, except that now each SPI command has 24 bits of data clocked in before chip select returns to the high position.

Thank you for watching this video on SPI communication with precision DACs. Please watch our other videos on precision DACs to learn more.