Hello. My name is Ken Schachter. And welcome to the F28379D LaunchPad technical overview with a demonstration of inter-processor communications. In this presentation, I will cover a technical overview of the F28379D LaunchPad. The technical details of the LaunchPad will be explored while demonstrating a basic dual core inter-processor communication technique for sending data between CPU1 and CPU2. This will help reinforce the understanding of the features included on the LaunchPad.

Additionally, various features of Code Composer Studio will be highlighted, such as dual core debug, real-time emulation mode, and displaying a waveform in a graph window. Specific information and support for the LaunchPad can be found in Control Suite. First, select Development Tools, then C2000 LaunchPad, and finally, LAUNCHXL-F28379D. The LaunchPad incorporates an XDS 100v2 emulator as shown on the left side of this photograph.

The USB mini B connector located in the lower left corner provides a JTAG communication link between the device and Code Composer Studio in addition to supplying power. Jumpers JP1, JP2, and JP3 can be removed if electrical isolation is required. However, the device will then need to be powered externally through the booster pack headers.

The booster pack headers are located on J1 through J8. LED D1 illuminates when power is applied to the LaunchPad. User programmable LEDs D9 and D10 are connected to GPIO34 and 31 respectively. The device is located in the center of the LaunchPad. And push button S3 is connected to the device reset line.

Jumpers JP4 and JP5 connect 3.3 volts and 5 volts to the booster pack headers J5 and J7 respectively. Header J21 connects to the ADC differential input pairs ADC in D0 through ADC in D3. The optional SMA connector points J19 and J20 utilize a differential amplifier to provide buffered signals to the ADC inputs ADC in D4 and ADC in D5 while operating in 16-bit mode.

Interfaces to the CAN, I2C, and QEPs are located on the right side of the launchpad using headers J11 through J15. The boot modes are set by switch S1. Details about the boot modes will follow on the next two slides.

When the device is reset, the peripheral interrupt expansion block, also known as the PIE block, and the master interrupt switch INTM are disabled. This prevents any interrupts during the boot process. The program counter is set to 3F FFC0, where the reset vector is fetched. In the boot code, the JTAG test reset line or TRST line is checked to determine if the emulator is connected.

If the emulator is connected, then the boot process follows the emulation boot mode flow. In emulation boot mode, the boot is determined by the EMU boot control register located in the PIE RAM. Specific details about the boot flow are then determined by the EMU key and EMU B mode fields in the EMU boot control register.

If the emulator is not connected, the boot process follows the standalone boot mode flow. In standalone boot mode, the boot is determined by two GPIO pins and the Z1 and Z2 boot control register located in the OTP. Specific details about the boot flow are then determined by the OTP key and OTP B mode fields in the Z1 and Z2 boot control register.

Boot mode switch S1 contains three individual switches. Position three is connected to the JTAG TRSTn line, the emulation boot mode, that is, when communicating with the debugger, this switch must be set to one. The other switch settings are for standalone boot mode.

In our demonstration, while in emulation boot mode, a CCS script will be used to set the boot mode to M0 RAM by populating EMU key to 5A and EMU B mode to 0A. The three main LEDs that we will be concerned with in this presentation are D1, which indicates the LaunchPad is powered on, and D9 and D10, which are connected to GPIO34 and GPIO31, respectively.

The demonstration will use LEDs D9 and D10 as visual indicators to show that the ADC A1 ISR and IPC1 ISR are running respectively. In the GPIO dot C file, GPIO34 is set as an output and initially turned off. Also, GPIO31 is configured to be controlled by CPU2 set as an output and initially turned off.

In default ISR_cpu1.c, GPIO34 will be toggled at a rate of 1 hertz. And in default ISR_cpu2.c, GPIO31 will be toggled at a rate of 5 hertz so that the slowly blinking LEDs D9 and D10 can be seen respectively. The LaunchPad includes a series of booster pack plug-in module connectors, which followed a TI booster pack pinout standard. During this demonstration, we will use a jumper wire to connect the output of DACOUTB, located on header J7 pin 70 to the input of ADCINA0 located on header J3 pin 30.

In this demonstration, on CPU1, the DAC output is configured to generate a sine wave form, which will be connected to the ADC input using a jumper wire. PWM2 will be used to trigger the ADC at a sampling rate of 50 kilohertz. ADCA1_ISR will then read and write the ADC result to IPC1 while toggling GPIO34, which is connected to LED D9 at a rate of 1 hertz.

Next, CPU2 IPC1_ISR will read the IPC1 data and store the ADC result in a circular buffer, while toggling GPIO31, which is connected to LED D10 a rate of 5 hertz. The sine wave form will be displayed in a Code Composer Studio graph window, while the device is running in real-time emulation mode. CPU2 IPC1_ISR will then write the next sine data point from the sine table to IPC0.

Finally, CPU1 IPC0_ISR will read and write the sine data point to the DAC and the process repeats. In CPU1 main, the CPU, ADC, DAC, and EPWM will be initialized. After initialization, CPU1 waits for CPU2 synchronization and then CPU1 enters an endless loop waiting for an interrupt from the ADC.

In CPU2 main, the CPU will be initialized. After initialization, CPU2 will synchronize with CPU1, then CPU2 enters an endless loop waiting for an interrupt from the IPC. In this demonstration, the DAC will generate a sine wave using a lookup table consisting of 25 points. In CPU1 ADCA1_ISR, the ADC result is read and written to IPC1. In CPU2 IPC2_ISR, the ADC result is read from IPC1 and stored in a circular buffer. Also, the next sine data point is written from the sine table to IPC0.

In CPU1 IPC0_ISR, the sine data-point is read from IPC0 and written to the DAC. Code Composer Studio is an integrated development environment, which supports all TI embedded processor families. It consists of a suite of tools that integrates the editing, code generation, and debugging into a single graphical user interface. It operates free without any restrictions when used with the TI XDS-100 JTAG emulation-based products, such as the C2000 LaunchPad.

And it is based on the Eclipse open source software framework. In the next few slides, I will explain how to build the project for the demonstration code from scratch, then I will run the project on Code Composer Studio using the F28379D LaunchPad as the target system. When using Code Composer Studio with a hardware system, a target configuration file needs to be created.

Selecting File, New, Target Configuration File will open a window for setting the file name. After selecting Finish, another window will open for selecting the connection type and device. Clicking Save saves the target configuration file. Next, a new project needs to be created for each core, CPU1 and CPU2. Selecting File, New, CCS Project will open a window for creating a project.

In this window, the project name, location, and device is selected. Under Advanced Settings, the linker command file is set to none since I will use the one that I've created for this project. For the project template and examples, I will select Empty Project, since I've created the source code. This project will make use of the F2837xD peripheral register header files. These header files can be found in Control Suite under Device, Delfino F2837xD, and then Supporting Libraries.

Next, we need to include these header files in the project. The build options must be set for each project, CPU1 and CPU2. The project build options are set by selecting the properties for the project. In the Compiler Include Options, the pound include search path for the peripheral register header files and user header files are set and saved. Now the demonstration will continue using Code Composer Studio.

In Code Composer Studio, I will click the Build button for each project. And we will watch the tools run in the Console window while looking for any error messages in the Problems Window The projects build successfully. The debug button will automatically open a debug perspective, connect and download the code to the target, and then run the program to the beginning of the main function. I will now select CPU1 Project and click the Debug button.

Notice the edit perspective has changed to the debug perspective. And the Debug window shows the target is connected. We are now at the beginning of the CPU1 main function. Next, I will connect the CPU2 and load the program.

We are now at the beginning of CPU2 main function. Since the emulator is connected, I will use the script for each CPU to set the EMU key and EMU B mode bit fields in the EMU boot control register so that the F28379d will boot in memory block M0 RAM.

I will now run each CPU in real-time emulation mode. Next, I will set the Memory Browser window to the address of the beginning of the circular buffer, ADC Buff, and enable it for continuous refresh. I will now open a Graph window to display the sine wave form and enable it for continuous refresh.

In the Debug window, notice that CPU2 is selected for debug. I will now change CCS so that CPU1 is selected for debug. And notice what happens to the Graph and Memory window. Recall that the circular buffer is running on CPU2. I will now change back to CPU2.

I will open an Expression window to view the IPC data registers and enable continuous refresh. While running in Real-time Emulation mode, I will remove and replace the jumper wire between the output of the DAC and the input of the ADC. Notice the changes in the graph window and memory window showing that the F28379D is running in real-time emulation mode.

Also, notice what happens to the IPC1 data registers containing the ADC results from CPU1. It is 0, showing that without the jumper wire, no new values are being converted by the ADC. This concludes the demonstration of the inter-processor communications on the F28379D LaunchPad. Thank you for watching. And I hope this presentation has been beneficial to you.