After capturing mixed-signal inputs, C2000 devices can quickly process and react to the sample data. At the center of their processing block is to C28x CPU, which is based on a 32-bit fixed-point architecture. Independent instruction and data buses allow the CPU to fetch instructions and write data simultaneously for efficient throughput. The processing power of the C28x CPU is further enhanced by the addition of hardware accelerators.

Native support for single-precision floating-point math is provided by the Floating-Point Unit, or FPU. Common floating-point functions are further accelerated by the Trigonometric Math Unit, or TMU. And common fixed-point functions are accelerated by the Viterbi Complex Math and CRC Unit, or VCU. To demonstrate the performance contributions of the hardware accelerators, we will compare the cycle times required to execute a sine function from the C2000 software libraries.

The native C28x CPU requires 46 cycles to calculate a fixed-point sine value, whereas the FPU requires only 37 cycles to calculate a floating-point sine value. Further acceleration is provided by the TMU which requires only 4 cycles to calculate a floating-point sine value.

The square root function also shows significant improvement in processing time when using the accelerators. 63 cycles are required for the C28x CPU, 28 cycles for the FPU, and only 5 cycles for the TMU. Hardware acceleration is also effective for fast Fourier transform calculations. Consider the library benchmarks for a complex FFT calculation on 1,024 points. The C28x CPU take 705 microseconds to complete the transform, while the FPU takes 266 microseconds and VCU-II takes only 70 microseconds.

The magnitude from this same complex FFT is calculated in 93 microseconds using the FPU compared to 26 microseconds using the TMU. And finally, that phase is calculated in 292 microseconds using the FPU compared to 36 microseconds using the TMU.

As suggested by its name, the VCU also includes specialized support for Viterbi and CRC functions for speeding up communication applications. Two parallel Viterbi butterfly operations can be completed in two cycles, and Viterbi traceback operations are completed in three cycles per stage.

CRC calculations take approximately 1 and 1/2 cycles per message byte, which means that the CRC for a 128-byte message can be calculated in about 192 cycles. Supporting the C28x processing hardware is 0 wait state RAM, operating in up to 200 megahertz and nonvolatile flash with read access of up to 50 megahertz.

The internal storage capacity can also be supplemented through the addition of external memory. External SRAM is capable of providing 90 megabytes per second of throughput, and external SD RAM is capable of providing 50 megabytes per second or throughput.

The Control Law Accelerator, or CLA, is an independent floating-point processor that can be programmed for a variety of purposes in the application system. When used as a co-processor, the CLA can offload calculations from the CPU through inner processor messaging. And when used as an autonomous processor, the CLA can execute its own full-time thread in the background.

The Direct Memory Access controller, or DMA, is used to perform background data transfers without CPU overhead. For example, the DMA can be used to transfer large blocks of data between internal and external memory or in systems that use the ADC. The DMA can transfer ADC results entering memory buffer and trigger a system interrupt when the buffer is ready for CPU analysis.

For maximum computing power, the F2837x series of devices include multi-core variance with two complete and independent processing subsystems, each having access to private and shared memory. The multi-core architecture is capable of supporting both parallel and distributed processing modes of operation.