Hello, everyone. Welcome to this Texas Instruments training video. My name I.K. Anyiam, and today I'm going to introduce the topic of TI Generation II and Generation III LVDS SerDes technology. This will give a quick overview of the architectures of our Gen I, Gen II and Gen III SerDes. Gen I devices typically have 24 bits of parallel RGB data being serialized at four different data pairs, and have one differential clock pair and the control running in parallel. It's typically used to send display data, but it can also be used to set high amounts of data-- for example, in AFE boards or DAC boards. Gen II devices take this serialization one step further by serializing the data and embedding the clock into a single differential pair with the control running in parallel.

Finally, Gen III takes it even further by serializing the data and embedding the clock and the control onto a single differential pair. These devices offer various features, but the most apparent feature of our Gen II and Gen III SerDes is the embedding of the clock and the data onto a single differential pair. The fact that you have a single differential pair instead of four or more differential pairs greatly reduces the footprint of the PCB, makes it easier to lay out, allows the use of smaller connectors, reduces the EMI due to less new lanes being transmitted, and extends the reach of the cable by at least twice that of Gen I devices.

A more technical benefit of this feature is the elimination of receiver skew. For example, with Gen I devices, typically you'll have 28 bits of parallel RGB data getting serialized down to four LBDS lanes with seven bits per lane, and one LVDS clock lane. The receiver will strobe in seven bits per LVDS data pair per clock cycle with internal clock running at seven times the clock frequency. Ideally, [? a strobe ?] in the middle of each bit, like in this diagram, but since the data and clock are sent on separate pairs, pair-to-pair skew could potentially cause the receiver to strobe incorrect pair values.

There is some margin, but designers need to focus on loss, jitter, and perform complex calculations that include strobe positions, pulse positions, and other parameters to calculate the receiver skew margin to ensure that their system performs properly. Another benefit is improved system reliability at reduced EMI with RBS encoding. In Gen I devices, stacked display images can include many of the same color bits, which can create DC wander and impact the signal quality, along with creating EMI beats. The RBS encoding randomizes the data and scrambles bit positions to remove static patterns and ensure transitions, and then DC balances the signal to allow AC coupling of the length to provide isolation.

The end result of this encoding is less shear and more spreading of the special content of the transmitted data for reducing EMI. It also helps extend the length of the cable that you can use. EMI is a key issue for cables over 1 meter with Gen I devices which do not have this encoding scheme. Another benefit of Gen II and Gen III devices is improving conditioning with transmit de-emphasis and receive equalization. Here's an example of a series chipset that illustrates these features. The serializer has transmit de-emphasis and the deserializer has an equalizer, which includes a test point for testing the equalized signal before deserializing it.

On the transmit side, de-emphasis de-emphasizes the low frequency content of the signal. This is because the cable acts like a low pass filter, and the signal's high frequency content will get attenuated after traveling through it. So if you de-emphasize the low frequency content of the transmit, when you get to the A receiver, it balances out, and you can still identify transitions. On the receive side, equalization further manipulates the signal to compensate for losses and the receiver can still receive a good representation of the original transmitted signal.

Here are some illustrations emphasizing the benefits of de-emphasis and equalization. As you can see, with both of these features, you will have a more open eye, less jitter, and it can travel a farther distance than without these features. Which brings me to the last feature I want to introduce-- extended cabling. With Gen I devices, cable length was heavily limited by peer-to-peer skew and cable attenuation.

The features that I just talked about that address these issues help extend the cable in the Gen II and Gen III series by more than twice that of Gen I. This slide should serve as a starting point when selecting the appropriate cable selection for a given system. Other impedance-controlled cables and connectors can be used to achieve various lengths depending on their loss characteristics.

Finally this table gives a nice summary of what I just talked about, and some other features, like express machine clocking and outputs the rate control for reduced EMI, bi-directional communication for control signals, and self-testing modules for easier debugging. Here's an overview of our current Gen I, Gen III and Gen III series portfolio where you can select the chipset based on desired resolution.

For Gen II and Gen III specifically, this slide highlights the different input interfaces and operating pixel clock frequencies. For additional resources, please reference our world famous LVDS Owner's Manual and our various application notes. Please also visit our EVM and products page for a nice selection of EVMs and devices. You may also visit our E2E form and ask any question about these devices, and receive a prompt response within 24 hours. Thanks for watching.