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Welcome to this TI Training. My name is [? Emanuel ?] [INAUDIBLE]. And in this video, we will find out together what are the specs to look for, where designing power distribution for SoCs and FPGA applications.

Microprocessors and programmable logic requires several voltage supply rails. Often these rails require accuracy and tight regulation other than sequencing requirements. It's then of key importance to identify those specs and their challenges in order to address them with the right power devices.

In this video, then, we will talk about the SoC power requirements, giving you first a system overview, and then digging into typical SoC and FPGA specification. We will then identify what are the challenges. And we will see how the DC and AC accuracies are the most difficult to address. Then we will go through a simple example of comparison between two devices in the TI portfolio.

A typical system on chip configuration-- and its supply rails will look like in this example. We will find most likely a core voltage, which is necessary in order to power up the processing unit; an analog voltage for the analog circuitry; and the I/O's voltages usually placed between 1.5 and triple and tripled in an auxiliary voltage in order to power up the all the auxiliaries, like PLL, peripherals, and their control units.

These rails must be derived by an intermediate power source, which usually is presented and identified as a 12-volt, 5-volt, or 3.3-volt voltage rate. Each one of these options presents pros and cons. And, for example, if we take into account the 5-volt range, it will have a fairly high efficiency conversion to the point of load, while the input current would be higher compared to the 12-volt rail, which instead has a lower efficiency conversion to the point of load, and possible duty cycle limitation due to the low conversion ratio from, for example, 12-volt to 1.2.

Also, 3.3-volt as intermediate rail is a valid option, because of the higher efficiency in the conversion to the point of load. But also, it presents the highest input currents, and there are fewer available parts due to the minimum Vin range.

Here are list Xilinx Xilinx 7000 system [INAUDIBLE] system on shipped voltage rates, with their accuracies and their estimated current consumption, using the Xilinx power estimator. Considering the VCCINT rail, we can figure out how challenging it is to satisfy the required plus/minus 50 millivolt accuracy, not only in a DC domain, which still needs to be properly addressed, but especially in the AC, since one could encounter low transient of 5 ampere or so, depending on the final application.

Its important to identify the amount of maximum tolerances that a power converter must exhibit in order to comply with the needed specifications. We can start from superimposing static and dynamic tolerances for our [INAUDIBLE] analyisis. These are respectively due to the AC and DC variation of the operating conditions, input voltage, and [INAUDIBLE] out.

Let's then dig in the factors which contribute to the static tolerances. An SMPS is a closed-loop regulated system. So in terms of DC error, we can identify as influencing parameters, the reference voltage-- also called Vref accuracy; the feedback divider resistors tolerances; the load and line regulation due to the error amplifier's finite gain, which is expressed often as a percentage of the output current for the load regulation, and input voltage for the line regulation; and last but not least, the non-ideal Vout sensing due to the PCB traces effect, also called uncompensated DC losses.

A brief calculation can make us notice how these factors played their role in the total static accuracy. The formula used in this computation results from the up node highlighted in the link. Since line and load regulation depend on the input voltage and output current, these contributes must be added on top of these results.

In each of the four datasets, we have tweaked one parameter to see their effect. We can see that the direct impact of the reference voltage accuracy-- which is additive in the formula-- plus the influence of the resistor divider, can significantly improve the accuracy, leaving more margin to the remaining dynamic tolerances.

The last effect to take into account, and actually to avoid, is the effect of the DC losses. The DC losses are and then the voltage drop due to the known ideal sensing. And this issue can be reduced by the mean of remote sense. That means that the feedback of the error amplifier must be directly connected to the FPGA core supply pins, or by the use of the wide and thick copper traces, which reduce the output resistance of the power supply. And the power supply should be placed as close as possible to the FPGA, or system on shipped supply unit, because shorter traces reduce resistance, as well as inductive loops.

This is a typical example or situation where this problem of the DC losses has been properly addressed, because the Xilinx Zynq 7000 series, of course, has more than one pin for the VCCINT and VCCPINT voltage rails. So the problem here is which pin I should sense, and how should they get to the inner VGA pins of this power supply?

Well, in this case, the TPS62480, which is a dual phase, but converted with 6-ampere maximum output current, has been placed as close as possible to the FPGA by using wider traces to minimize DC losses. This has been possible only because the approach for the power distribution for this project has been done through discrete devices, one for each or two voltage rails.

Let's make another calculation example using actual devices. The TPS62135 for the Altera MAX 10 core voltage of 1.2 volt at 4 ampere maximum load, and with 12-volt input voltage; and the TPS62480 for the Xilinx Zynq 7000 1-volt core voltage at 6-ampere maximum load with 5-volt input voltage.

Using these information, the load regulation, the voltage reference value and accuracy, which are found in the datasheet, and a 0.1% tolerance resistors for the feedback divider, one can estimate the DC error using the already mentioned formula. These result in an amazingly positive result, since more than 3.7% out of the 5% required accuracy is left to the AC margin, allowing smaller [INAUDIBLE], because of less necessary filtering action during the load transient, for example.

Worth to mention is that the Vin regulation contribute is not needed to be added on top of the formula, because the intermediate rail-- the input voltage-- is also supposedly coming from a preregulated converter.

Talking about AC tolerances, we still need to identify which are the factors that contribute to their mount, since in our worst-case analysis those amounts get added on top to the DC variations. In this particular application, the input voltage is generated supposedly by a preregulated SMPS. So is mainly the load transient, the AC event causing output voltage variations. The influencing parameters are then the slope of the output load during a load transient, and its step size; the control topology of the power converter-- for example, voltage mode, current mode, hysteretic control, or DCS control; and the entity of the output filtering.

The DC/DC converters from the TPS 62000 series from Texas Instruments do not need external compensation network, enabling an faster design and debug cycles. This is possible only because the compensation is designed and realized on silicon internally in order to minimize the transient response in relation to the specific control topology in [INAUDIBLE] condition.

This approach leaves the choice of input to output filtering, inductor and capacitor, to the customer. Within specific and simple value tables, same guidelines find in each data sheet. Specifically for FPGA application, is important to design an effective power distribution network, which in case of discrete results, an easier task to do, thanks to the less [INAUDIBLE] introduced by TCPB traces. A common denominator in these kind of devices is the fact that there is no need of low frequency type bulk capacitor, because of the high bandwidth and highs which in frequency of those ICs.

These waveforms have been measured in a real applicative board, which is the one in the example shown before. The programmable logic has been configured to result in cycles of every load, followed by a standby state. With TPS62480, the designer has been able to obtain less than 30 millivolts to overshoot and undershoot, which means less of the percent of the DC voltage. With slow rate of 6-ampere per microsecond, and 2.5 per step size for the current.

Just a small note on the measurements. The currents-- the blue and green waveforms on the right plot-- for feasibility reason have been measured where the output of the SMPS splits to the VCCINT and VCCPINT core voltages, not at the BGA pins. Though the voltage waveforms have been measured right at one of the pins of the VCCINT-- the programmable logic core voltage-- which is the pin or the voltage that more sees the load transient effect. Hence, a bigger effect of the decoupling PDN.

In order to enhance the efficiency at light loads, many SMPS support a power-safe mode, which is implemented to pulse frequency modulation. This consists in decreasing the switching frequency at light loads by mean of the dynamic control load, reaching, hence, amazing and unbeatable efficiency values, even when your application is in standby mode.

Though the flip side of that is the ripple, and especially the DC error, that will increase because of the control pulse frequency modulation, since it is very similar to [INAUDIBLE] mode. This will introduce the concrete risk of not satisfying the narrow accuracy requested for the associated voltages. So in most of the cases, the suggestion is to choose devices where the PWM mode can be forced by mean of an additional pin.

On the FPGA support page on the TI's website, you can find a complete guidance tool to select the devices for a complete solution for a large variety of microprocessors, microcontroller, SOCs, and FPGA. The suggestions for each voltage rail of a selected chip are comprehensive of PMIC and discrete approach. And they are tailored on a different application specification. That means the input voltage and the load current of the chip.

With this, we are done for this video. I hope you enjoyed it, and that it will be useful for your present and future projects. See you at the next one, and enjoy your design. Ciao.