Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 2
Let's take a deeper dive into the high speed multi-channel JESD204B compliant clocking solution. You will learn about the architecture and performance results with the 12-Bit, Dual 3.2-GSPS or Single 6.4-GSPS, RF-Sampling Analog-to-Digital Converter (ADC).
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Hello, everyone. This is Ajeet Pal, systems engineer from the systems team of Texas Instruments. Welcome back to the part two of the three series on "Synchronization of High Speed Multichannel JESD204B Complaint Clocks" used in testing measurement and [INAUDIBLE] and defense sector.
In this part of training, we will learn about the proposed clocking solution, reference design, and its performance reserves. This TIDesign objective and device selection. The objective of the TIDesigns are the clocking solution, search support, latest high speed giga samples per second are RRF JESD data converters.
Systems that support wider input bandwidth signals, hence need low jitter. Device clock and SYSREF space should be acting adjustable. The clocking solution should provide the FPGA clocks also. In TIDA-01021, TI reference design, following major parts of selecting where LMX2594 is appearance synthesizer responsible for device clock and SYSREF generation for the data converters.
LMX04828 is a [INAUDIBLE] cleaner with dual loop feelers responsible for FPGA clocks and control signals to LMX2594. And LMK6182 is a programmable reference source. This is the one picture of the TIDA-01021 a reference design. It has a feature of multi-channel JESD204B compliant clock generation up to 15 gigahertz.
The provided clocking solution is shielded for high dynamic range and high SNR multichannel AFP signal chains. It also has a configurable phase synchronization to achieve low channel to channel skew. The provided clocking solution can be interfaced with the TI existing or upcoming high-speed data converter EVM, along with the FMC adapter card or slight modification on that.
This is the high-level block diagram of the TIDA-01021 multichannel clocking forward. In this solution, two LMX2594 receive the reference signals from LMK6282 via LMK04828. Reference frequency of the system is based on the SYSREF requirement and generated by the LMK6182.
Both elements 2594 can work in SYSREF master or repeater mode and generate the synchronized T clocks and SYSREF output after getting a sync signals from LMK04828. LMK04828 is responsible for generating FPGAs, reference, and core clocks, and SYSREF also, SYSREF request, and sync signals to LMX2594.
After the sync signal, LMX2594 [INAUDIBLE] synthesizer RF out signals further can be tuned using massive operation of reducing the delay. In this solution, LMK04828 is configured in PLL mode to generate FPD clocks and control signals to LMX devices. And LMX2594 devices are configured as master mode to generate the SYSREF output by a SYSREF request control signals from LMK04828.
This clocking board has several other options from each subsystem. It has multiple input reference and clock in both where it can take input reference signal also from on-board VCX0, programmable reference signal using LMK6182 or external input to work LMK04828 in PLM mode and can take clock in 0 or clock in one input signal to work LMK0428 in distribution or bypass mode.
On the clock output site, can have device clock out from LMX2594 or LMK04828. It has on-board temperature sensor to see the temperature throughout the board. Also has various DC power options like from DC/DC only LDOs only or combination of both. And TID1021 uses of combination of DC/DC and LDOs for better performance and optimized power solution.
This design has two sets of JESD204D compliant FPG clock has it connects to two different FPGA cards. Depends on the clock requirement and input signals, user can configure this board for their requirement. This design also contains one more board which is called FMC adapter card. This card is responsible to interface between ADC or DAC EVM, and FPGA or capture card. This also bypass FPG clocks from the the DAC and the EVM and provides FPGA clocks from TIDA-1021 clocking board.
Now we will look on the performance of the proposed clocking solution. This test is to show the phase noise performance of LMX2594 on TIDA-01021 board with reference signal from LMK6182. Here, LMK6182 is generating 100 megahertz as os in signal to LMX2594 and LMX2594 has a phase trajectory frequency of 200 megahertz.
After measuring the phase noise of the data of the LMX2594 at various frequency, the jitter is around 58 femtosecond, 52 femtosecond, and 60 femtosecond at 3.5 gigahertz, 9 gigahertz, and 15 gigahertz output frequencies respectively. And these values are close to the LMX adjusted specifications.
Now the actual implementation of the clock to see the clock to clock skew are delayed between the clocks. Reference frequency is changed to equal to the SYSREF frequency, which is 33.75 megahertz for 2.7 gigahertz device clock. In this set up, oscilloscope is connected to all four board of LMX2594 and measure the clock to clock delay.
And the major device clocks to clock skew is around 5.6 picosecond, 7.6 picosecond, which is good for any low skew system. The phase aligned JESD204 compliant clock solution is interfaced with two number of ADC12DJ3200 to seed the analog channel to channel skew and SNR performance of the data converters.
Then using the high performance clocks, measured SNR is around 55.7 DPFS at 997 megahertz input frequency, which is comparable to the ADC EVM performance. And the major SNR channel to channel skew is better than 10 picosecond, hence the provided clock solution is validated with the high speed ADC and shown the good SNR performance and mighty channel synchronization.
So in summary, the provided multichannel is good suited design for the high speed [INAUDIBLE]. In the next part of this training, we will discuss about the height and count clock different designs. Thanks for watching.
This video is part of a series
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Clocking solutions for high-speed multi-channel applications
video-playlist (6 videos) -
How to synchronize high speed multi-channel clocks
video-playlist (3 videos)