Hello, and welcome to the I squared C protocol overview video from TI's Precision Lab. In this video, we'll discuss how the protocol is implemented at the most basic level. And we will discuss some of the key design parameters for implementing I squared C.

The inter IC interface, I squared C, was created in 1982 to address the need for a simple, robust, low-cost protocol for communicating between ICs while using the least amount of pins. As the variety of peripheral parts increased and the benefits of the I squared C interface became obvious to system designers, the I squared C interface rapidly increased in popularity, and was widely adopted shortly after it was released as a standard.

There are an enormous range of devices that use the I squared C communications interface, and system designers are only limited by their own creativity. Here are just a few types of devices that can be used-- IO expanders, temp sensors, light sensors, memory, keypad scanners, pressure sensors, humidity sensors, ADCs, DACs, and a variety of other devices that use the I squared C protocol.

The I squared C bus is a bi-directional interface that uses a controller known as the master to communicate with the slave devices. The physical I squared C interface consist of a serial clock, SCL, and a serial data line, SDA. Both SDA and SCL lines must be connected to VCC through a pull-up resistor.

A slave may not transmit data unless it has been addressed by the master. Each device on the I squared C bus has a specific device address to differentiate between the other devices that are on the same I squared C bus. I squared C communication with the device is initiated by the master sending a start condition, and is terminated by the master sending a stop condition.

A high to low transition on the SDA line while the SCL is high defines a start condition. When a master has taken control of the bus by generating a start condition, no other master can take control of the bus until it is released by a stop condition.

A low to high transition on the SDA line while the SCL is high defines a stop condition. In between the start and stop conditions, the communication of data must be performed. The I squared C standard defines every I squared C data transaction in an eight-bit format, or sometimes called byte, with the most significant bit MSB at the beginning of the frame, and the least significant bit LSB at the end of the frame followed by either an acknowledge ACK, or a no acknowledge, NACK.

It is important to note that in these diagrams the bits, which we see as squares, are color coded to indicate if the master or the slave are controlling the generation of that bit. Gray colored bits, or squares, are controlled by the master, and white colored bits are controlled by the slave.

Multiple bytes sent simultaneously will be performed by repeating the clock pattern from bit 1 to 9, where the ninth bit is either the ACK or the NACK. Once the data transmission is sent, then either a stop or a repeated start condition will need to be initiated in order to establish if the bus is released or a new transaction will be initiated by the master.

One data bit is transferred during each clock pulse of the SCL. One byte is comprised of eight bits on the SDA line. A byte may either be a device address, register address, or data written to or read from a slave. Any number of data bytes can be transferred from the master to the slave between the start and stop conditions.

Data on the SDA line must remain stable during the high phase of the clock period. Here is an example of sending 1, 0, 1, 0, 1, 0, 1, 0, which is AA in hex, with an ACK. Changes in the data line when the SCL is high are interpreted as control commands such as start and stop.

Each byte of data, including the address byte, is followed by one ACK bit from the receiver. The ACK bit allows the receiver to communicate to the transmitter that the byte was successfully received and another byte may be sent. Before the receiver can send an ACK, the transmitter must release the SDA line.

To send an ACK bit, the receiver pulls down the SDA line during the low phase of the ACK/NACK related clock period, period 9. When the SDA line remains high during the ACK/NACK related clock period, this is interpreted as a NACK. Set up and hold times must be taken into account.

There are several conditions that lead to the generation of a NACK. One, the receiver is unable to receive or transmit because it is performing some real-time function and is not ready to start communications with the master. Two, during the transfer, the receiver gets data or commands that it does not understand. Three, during the transfer, the receiver cannot receive any more data bytes. Four, the master receiver is done reading data and indicates this to the slave through a NACK.

Here's the general procedure from master to slave communications where the master either writes or reads data from a slave. Here are the steps when a master wants to send or write data to a slave. One, master transmitter sends a start condition and addresses the slave receiver. Two, master transmitter sends data to slave receiver. Three, master transmitter terminates the transfer with a stop condition.

Here are the steps when a master wants to receive or read data from a slave. One, master receiver sends a start condition and addresses the slave transmitter. Two, master receiver sends a request register to read the slave transmitter. Three, master receiver receives the data from the slave transmitter. And four, master receiver terminates the transfer with a stop condition.

The bit and condition patterns for generating read and write transactions are defined by the following. Gray boxes indicate it is controlled by the master. White boxes indicate that it is controlled by the slave. Gray/white boxes indicate that the bit can be controlled by either the master or the slave.

There are three conditions. One, start condition, two, stack condition, and, three, repeated start conditions.

Address bits are designated by the letter A. Register address bits are designated by the letter B. Data bits are designated by the letter D.

The read/write bit can be either a write, which is shown as a negated W, and is performed when the bit is 0, or a read, which is shown as an R, and is performed when it is a 1. The ninth bit is always either an acknowledgment, which is represented as A, or ACK, and is 0, or a not acknowledgment, which is represented as a negated A, or a NACK, and is a 1.

Here is a bit and condition pattern for writing two bytes to a slave. The master will generate a start condition on the bus. The master generates a slave seven-bit address, as well as the last bit, which is the read/write bit. In this case, it is a write, so it is set to 0 and is represented by the negated W.

Assuming there is a slave on the bus with that address, then that slave will generate the ACK. The master will then send eight consecutive register bits, or the byte, and the slave will then acknowledge the receipt of those bits by generating an ACK. The master then sends a second consecutive set of bits, the second byte, then the slave will acknowledge again, letting the master know it has received it. The master then generates the stop condition to terminate the transaction.

Here is a bit and condition pattern for reading two bytes from a slave. The master will generate a start condition on the bus. The master generates the slave seven-bit address, as well as the last bit, which is the read/write bit. In this case, it is a read, so it is set to a 1 and is represented by the letter R. Assuming there is a slave on the bus with that address, then the slave will generate an ACK.

The slave will then send eight consecutive register bits, or one byte, and the master will then acknowledge receipt of the bits by generating an ACK. The slave sends the second set of consecutive bits, the second byte, then the master will not acknowledge, or NACK, letting the slave know it's finished receiving the data. The master then generates the stop condition to terminate the transaction.

These two patterns represent the most basic of read and write transactions between a master and a slave. More complicated read/write transactions or patterns are covered in the I squared C example-- Read/Write For Internal Registers training video.

That concludes this video. Thank you for watching. Please try the quiz to check your understanding of this video's content.