I2C translators overview
This video is part of the TI Precision Labs - I2C curriculum. In this training we discuss the I2C translators, which are used to facilitate communication between devices operated at different supply voltages. The training discusses the basic theory of operation of these devices and common concerns with their usage
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Hello, and welcome to Precision Labs training video on I squared C translation. In this video, we'll discuss the need for translation in I squared C systems, how it's implemented in hardware, and how it impacts the system.
I squared C uses an open drain driver with an input buffer, which supports bidirectional communications. This means the pull-up resister is completely in control of generating the high signal. If you aren't familiar with the I squared C hardware layer, please see the I squared C Hardware Overview video for additional information and training.
In this diagram, we see the two devices have different VCC voltages, VCCA1 and VCCB2. This means that their digital logic levels are different, and we need to do translation from one voltage level to the other, it's often called a voltage level mismatch.
Here's an example. VCCA1 is set to 5 volts and VCCB2 is set to 3.3 volts, which VCC should the pull-up resistor be connected to. If the pull-up resistor is connected to VCCB2 at 3.3 volts, then the voltage on the bus will never reach the VIH of the device on VCCA1, which is 70% of 5 volts, or 3.5 volts.
In other words, the device in the 5 volt bus will not see the logic high for the pull-up resistor in the device connected to 3.3 volts. If the pull-up resistor is connected to VCCA1 at 5 volts, then that indicates that the device with the VCC at 3.3 volts will be exposed to a voltage higher than its operating voltage. This could cause damage to the lower voltage device, and the voltage levels on the VIL will still be shifted.
It is clear that this voltage level mismatch must be fixed. And that is done with a translator, which is sometimes called a level shifter. Typically, translation for I squared C is done using a pass FET architecture, which provides voltage level isolation while providing a method to pass a low signal. But it does not provide a means to isolate bus capacitances.
We need to look inside a pass FET translator to understand how it works. In this example, the PCA9306 is used with the master on side 1 and the slave on side 2. Note, it does not have to be that way. Remember that I squared C is bi-directional, and the master and slave locations can be swapped.
Only one of the two lines needed for I squared C communications is shown, but the physical implementation is identical in all observations pertaining to both SCL and SDA. Let's first consider the idle state, where both sides are high and either side of the translator is being pulled low.
VCCA1 is equal to 2.5 volts and VCCB2 is equal to 5.0 volts. All the FETs are off. Side 1 of the bus will be pulled to 2.5 volts via RPU1. And side 2 of the bus will be pulled up to 5.0 volts by RPU2.
There is a voltage on the translator's pass FET gate labeled VGATE. And in this example, it is 2.5 volts. Let's take the instance where the master pulls low. As side 1 starts to pull low, the CBUS is getting discharged, and we start to produce a state where the voltage differential is created between VGATE, which is set to 2.5 volts, and VSOURCE, which is the bus voltage.
As VGS increases past the threshold voltage of the pass FET, which is typically 0.7 volts, it would quickly turn on. It is easy to see that when the master pulls low, then the pass FET will turn on and both sides, 1 and 2, are low through the pass FET.
The pass FET does have a finite resistance, and it will affect the VOL seen at the slave because there's an IR drop. Once all of the values of the pull-up resistor and FET resistances are known, then you can calculate the voltage seen at the slave input. The voltage at the input of the slave device is not like a true VOL of a buffer. Because the voltage on side 2 of the translator varies depending on the resistance values of all the pull-up resistor on both sides of the translator, and the resistance of all the FET devices in the circuit.
If multiple translators are used in either series or parallel, then the calculations can become unwieldy. And we recommend using a simulator, such as TI Tina.
Here is an example. There are three buses which are separated by their voltage nodes using two series translators. Bus 1 is at 5 volts, bus 2 is at 3.3 volts, and bus 3 is at 2.5 volts. When the master pulls low, then both pass FETs on the translators are turned on to relay the low signal to each bus.
The example circuit was redrawn in TI Tina. Pull-up resistor RPU1, RPU2, and RPU3 are set to 1.5 k-ohms. And the slave and translators pass FET resistances are determined by looking at each respective data [INAUDIBLE] specification. The master's pull-down FET resistance is 130 ohms. The translator pass FET resistance is 6.3 ohms typical.
Given these parameters, we can input the representative circuit parameters into TI Tina to see how the effective VOL changes from bus to bus. The results shows that VOL at bus 1 is 740 millivolts. At bus 2 is 758 millivolts. And at bus 3 is 765 millivolts.
The I squared C standard states that the input low voltage, or VIL, of a compliant device is 30% of VCC. That means VIL for bus 1 is 1,500 millivolts. VIL for bus 2 is 900 millivolts. And VIL of bus 3 is 750 millivolts.
For this given circuit, we see VOL3 violates the required VIL3 of 750 millivolts. Either the pull up resistors or how the translators are connected needs to be changed to ensure VOL well is lower than VIL, which ensures proper operation. Due to the nature of the translators pass FET architecture, it is clear that pull-up resistor values and the pass FET series resistances can adversely affect VOL, and great care must be taken to ensure proper operation of the interface.
Similarly to VOL, the rise time on the bus can also be adversely affected when using translators. Here is the previous example where the master has pulled the bus low. Bus 1 has a bus capacitance called CBUS1, and is due to the capacity of the master, the capacitance on [? side ?] 1 of the translator, the capacitance due to the parasitics on bus 1 from the traces on the bus. Bus 2 has a bus capacitance called CBUS2, and is due to the capacitance of the slave, capacitance of side 2 of the translator, and the capacitance due to the parasitics on bus 2 from the traces on the bus.
It's important to note that when the translator's pass FET is on, CBUS1 and CBUS2 are effectively in parallel with only a small resistance separating them. Let's take the instance where the master releases the low. As the bus voltage starts to rise due to the pull-up resistor, the VGS of the pass FET will start to decrease and the resistance to the FET will increase.
Keep in mind that there is still a resistive connection between bus 1 and bus 2 until the VGS approaches the threshold voltage, which is on the order of 0.7 volts. At that point, the two sides are charged up to their respective VCCs by their respective R pull-ups.
The max rise time is somewhat complicated to calculate because it includes CBUS1, CBUS2, RPU1, RPU2, and the turn-off characteristics of the pass FET. Fortunately, the I squared C interface is a robust interface, and translators are often used without any type of adverse effects to max arise time and VOL.
Usually, adjusting the pull-up resistances to each bus will most times solve the problem seen on the bus. Translators are a cost effective way to perform translation and are used as long as bus capacitances don't violate the I squared C standard based on the mode of operation used. This interdependence between pull-up resistance and bus capacitance can often be avoided by using a buffer which separates the bus capacitance and the associated pull-up resistances on each side of the buffer.
For more information about I squared C buffers, please watch the I Squared C Buffer Overview video, or read the Why, When, and How to Use I Squared C Buffers application report.
That concludes this video. Thank you for watching. Please try the quiz to check your understanding of this video's content.
This video is part of a series
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Precision labs series: I2C
video-playlist (4 videos)