I2C buffers overview
This video is part of the TI Precision Labs - I2C curriculum. In this training we discuss I2C buffers, in which applications they are needed, and how they are able to re-drive bi-directional, open-drain communication.
Resources
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download Learn more about why, when, and how to use I2C buffers
Hello, and welcome to the Precision Labs training video on I squared C buffers. In this video, we'll discuss the need for buffers in I squared C systems, how it's implemented in hardware, and how it impacts the system. The I squared C bus is a 5-directional interface that uses a controller, known as the master, to communicate with a single slave or multiple slave devices. Each device on the I squared C bus has a specific device address to differentiate between other devices that are on the same I squared C bus.
The physical I squared C interface consists of the serial clock, SCL, and the serial data line, SDA. Both the SDA and SCL lines must be connected to the VCC through a pullup resistor. The size of the pullup resistor is determined by the amount of the capacitance on the bus and the max VLL used on the I squared C bus.
It is important to note that the capacitance on the bus, CBUS, includes the PCB capacitance, the master's capacitance, and each of the slave's capacitance. Both the SDA and SCL lines of the I squared C interface have their own bus and have their own separate and potentially different bus capacitance, CBus. This video discusses a single bus for simplicity's sake. But it will pertain to both the SCL and SDA lines. The single bus is meant to represent either SDA or SCL.
The I squared C interface has different modes of operation based on the max clock frequency of communication, which is referred to as f CLOCK MAX. Three modes are covered in this video-- Standard Mode, Fast Mode, and Fast Mode Plus.
The I squared C standard defines a variety of parameters for each mode of operation, but only four of the most important parameters are defined for this video, which are C BUS, t RISE MAX, V OL MAX, in I OL MIN. For Standard Mode, we have f CLOCK MAX at 100 kilohertz, C Bus MAX at 400 picofarads, t RISE MAX at 1,000 nanoseconds, V OL at 0.4 volts, and I OL at 3 milliamps. For Fast Mode, we have f CLOCK MAX at 400 kilohertz, C BUS MAX at 400 picofarads, t RISE MAX at 300 nanoseconds, V OL at 0.4 volts, and I OL at 3 milliamps. And for Fast Mode Plus, we have f CLOCK MAX at 1,000 kilohertz, C BUS MAX at 550 picofarads, t RISE MAX at 120 nanoseconds, V OL at 0.4 volts, and I OL at 20 milliamps.
These parameters are used to select pullup resistor values and to determine if a buffer is needed in the system to meet the I squared C standards. The max rise time specification, t RISE MAX, for SCL and SDA is controlled by the IC time constant created by our pullup and C BUS and is defined as the amount of time it takes to transition from VIO to VIH. The maximum size of the pullup resistor for a given mode of operation is defined by equation 1, which t RISE must never be exceeded for any given bus capacitance in C BUS, where t RISE MAX must never be exceeded for any given bus capacitance C BUS, thus setting the upper limit of the pullup resistance value.
The minimum pullup resistance. R Pullup Min, is defined by the VOL Max, which is the voltage-induced cross the pull down fit when turned on, having a specified IOL Min passing through it. This is effectively defining the max RDS on of any FET on the bus. Knowing the VCC, and the VOL MAX, and the IOL MIN, we can then define the minimum pullup resistance needed to ensure VOL is never exceeded. See equation 2. This bounds the lower limit of the pullup resistor value.
The I squared C interface can support having hundreds of slave devices on the bus, just based on the number available slave addresses. But it becomes clear that if each device can have as much as 10 picofarads of capacitance, the number of slaves on the given bus for mode of operation will be limited by C BUS MAX. This means a method of subdividing a single bus and its bus capacitance into multiple buses is required in order to meet the I squared C timing requirements.
Fortunately, the I squared C buffers do just that. They take one bus that has a bus capacitance of C BUS and subdivide it and isolate it into two buses-- capacitance C BUS 1 and C BUS 2. Subdividing the bus capacitances requires the need for separate pullup resistors to generate the logic high on each bus, thus the need for R pullup 1 and R pullup 2. Bus 1 and bus 2 must both follow the I squared C standards for t RISE MAX, C BUS MAX, VOL MAX, and IOL MIN for the mode of operation used.
For more information on implementing, selecting, and using I squared C buffers, please read the why, when, and how to use I squared C buffers application report.
That concludes this video. Thank you for watching. Please try the quiz to check your understanding of this video's content.
This video is part of a series
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Precision labs series: I2C
video-playlist (4 videos)