Hello, and welcome to The Logic Minute. In this video, I will discuss the JTAG interface commonly used in most enterprise communications and industrial sectors. In addition, I will discuss voltage level translation implementations for the JTAG interface.

JTAG is named after the Joint Test Access Group that developed this hardware interface, which allowed boundary scan testing of embedded designs. The rack sever block diagram shown here employs JTAG interface while debug testing between different subsystems, example, between CPU, memory, board control, and platform control hubs.

JTAG typically operates with four signal lines. The TCK is the Test Clock, or reference clock. TDI is the Test Data Input into the DUT, or the Device Under Test. TDO is the Test Data Output coming out of the DUT into the JTAG probe. TMS allows the user to select the device to test.

When the JTAG port and the debugger ship operate at different voltage levels, a level shifter is required to shift the I/O signal voltage to enable the two devices to communicate. There are multiple TI level shifter solutions that can be considered for JTAG level shifting.

JTAG level shifting can be accomplished by using a direction control level translation device like the AXC family. With its four independent direction pins controlling the direction of each of its four channels, the SN74AXC4T774 device enables low voltage translation between the JTAG probe and the debugger chip.

When board space is critical, or if level translation up to 5 and 1/2 volts is desired, an auto bi-directional level translation device can be used which offers the flexibility for level translation without the need for separate direction control pins. The TXB0104, shown here, provides low DC drive strength, making it suitable to interface between any two high input impedance channels.

Please come over to the E2E forums to ask other logic and translation-related questions. Thank you for watching.