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Hello, and welcome to the TI Precision Lab introducing settling time and update rates for precision DACs. In this video, we will be covering the differences between settling time and update time, how to calculate these times, and how to determine the maximum update rate for a precision DAC.

Firstly, we will discuss what we mean when we say settling time. The settling time of a DAC is the total time a DAC requires to transition from an initial output voltage, and to settle within a defined threshold of a desired final output voltage. The settling period begins when the DAC resistor ladder's switches latch a new digital value. This point is commonly called the LDAC pulse, where LDAC stands for Latch DAC, or Load DAC.

Some precision DACs feature an LDAC input pin to trigger the update, while others will internally trigger the LDAC event at the end of a digital I2C or SPI command. In the figure, we indicate the beginning of the settling time as the falling edge of the LDAC pulse. Unlike an amplifier, there is a digital delay from the time the target output code is programmed to the device and when the output starts to transition.

This is the time the internal logic of the DAC requires to latch the switches, which we call dead time. On most DACs, this time is on the order of tens of nanoseconds. Next, the output will enter the slewing phase of the transition. In this time, the amplifier is driving the output at the fastest slew rate it is capable of.

The output then enters the recovery phase. This is where the output is trying to recover from the overshoot caused by the slewing phase. Larger capacitive loads on the DAC output can increase the recovery time. And finally, the device enters the linear settling phase. In this phase, the output is approaching the final value. A threshold must be defined to determine when this phase ends.

In most product data sheets, we define the settling time as a limit in percentage, or as number of Least Significant Bits, or LSBs. For example, we may define the DAC as being settled when the output has reached plus or minus 2 LSBs of the final value. The sum of these periods is the total settling time of the device. Generally, the settling time is defined for a large output step, as that is usually the worst case. It is possible for DACs to settle in a shorter amount of time for smaller output steps, as the slew and recovery periods are shorter.

Now let's look at an example. This is the data sheet specification for settling time and slew rate for a precision DAC. Here, we specified that the range is plus or minus 10 volts, or 20 volts total, and that the step size is from 1/4 scale to 3/4 scales. This is a total step of 10 volts. We see that the slew rate for this range is 4 volts per microsecond.

Seeing as we have a 10-volt step, we can calculate that the slew time is 10 volts over 4 volts per microsecond, or 2.5 microseconds total. The total settling time is 12 microseconds. This means that 9.5 microseconds are attributed to dead time recovery and settling periods of the DAC output transition. Realistically, the dead time for most DACs is very short, so it is safe to assume that most of the 9.5 microseconds is the DAC recovery and settling period.

Now that we have covered the basics of DAC settling time, let's talk about the time it actually takes to update the DAC's digital input code. Here we see a typical DAC's timing diagram and table for an SPI interface. At minimum, the device will need at least one SPI command to update the DAC's value. For this device, we see that 24 bits are required to be sent from the master to the slave per SPI frame.

Note that there are some special timings shown on the diagram, tCSS and tCSH. These are found after a falling edge of chip select and before the rising edge of chip select. This means that there will be a little extra time required before and after the [INAUDIBLE]. We will need to handle these timings separately. Finally, there is the chip select high timing requirement. This is the minimum time the chip select can be held high before the next SPI transaction begins.

These different timing requirements can be summed as shown in this equation to determine the minimum time to update the DAC register. Recall that there were 24 bits of data, but the first half period of the first bit and the latter half period of the last bit had special timing limits. For this reason, we only multiplied the tSCLK value by 23. The values for tCSS and tCSH, as well as tCSHIGH, can be summed with the SCLK.

We can calculate the minimum update time as 498 nanoseconds, or about 2 million samples per second. Given that the settling time for this device is about 6 microseconds, we can say that the maximum update rate for the device is not limited by the digital interface, but by the settling time. That is not always the case, though.

Now let's look at the time it takes to update a DAC using another very common digital protocol, I2C. I2C relies on an addressing scheme that allows multiple devices to share a bus, so there is usually extra data that must be sent to the DAC to allow an update to occur. This device requires 4 bytes to update the DAC.

This device requires 4 bytes to update the DAC. First, there is the address byte, which is unique to this DAC and allows the device to be selected individually. Next, there is a command byte. This byte is usually used to address a single channel of the device, or to configure the device for a special kind of update. Finally, there are 2 data bytes that contain the desired update code.

After each of these bytes, there is an ack, or slave acknowledge. This SDA transition is created by the slave on the bus to acknowledge that the data was received, but this requires the master to provide an additional SCLK pulse. From a timing perspective, that looks like 9 clock periods per byte of data. The I2C transaction is started with a start or repeated start transition from the master, and ended with a stop transition. All of these have additional timing requirements.

I2C is more standardized than SPI, so the bus speed is limited to a few different values. Standard mode operates at 100 kilohertz, fast mode operates at 400 kilohertz, and fast plus mode operates at 1 megahertz.

For this example, our DAC is using the fast plus mode timing specifications. For each of the 4 bytes of data, there are 9 clock periods, plus the hold time after the start edge, plus the setup time after the repeated start or stop edge. In most devices, these have the same timing requirements. Finally, there is a minimum time where the bus must be idle between SPI transactions. By adding these values together, we can calculate the update time for this device is about 38.6 microseconds, or 26 kilosamples per second.

Here we have two figures showing two types of update rate limits. On the left, we have an example of a DAC where the settling time is greater than the digital interface update time. But you can see that we have enough time during the settling period to write the next code to the device. In this case, the DAC sample rate is determined by the settling time.

On the right, we have an example of a DAC where the interface update time is longer than the settling time. This means the maximum DAC update sample rate is limited by the interface update time. The maximum sample rate is calculated by taking the inverse of either the settling time or the digital update time, whichever is longer.

Now let's look at a device and try to determine if its maximum update rate is limited by the settling time or the digital interface update time. Let's consider an MDAC, the DAC7811. Recall that an MDAC has a much faster settling time due to its unbuffered current output. In the specification table, we see the settling time is 200 nanoseconds.

In the timing table, we can find all the values required to calculate the minimum update time for its SPI interface. Doing that, we find that it'll take a minimum of 353 nanoseconds. So for this device, the update rate will be limited by the SPI interface.

Those are the basics of update time and settling time. In conclusion, the maximum sample rate in which a DAC can be updated could be limited by either the interface update time or the analog settling time. To determine the max sample rate, we must first calculate the digital interface update time by summing the various timing limits in the product's timing specification table.

Then we must find the settling time value of the DAC output by finding the specification in the electrical characteristics table. Finally, we take the inverse of the larger of the two time periods to determine the max sample rate.

Now let's do a short quiz on these topics to test our knowledge. Question one. If a DAC has an SPI interface that takes 2 microseconds to update, but the output settles in 4 microseconds, what is the fastest sample rate the device can have? A, 250 kilosamples per second, B, 500 kilosamples per second, C, 166.6 kilosamples per second, or D, 200 kilosamples per second.

The answer is A, 250 kilosamples per second. In this case, the output settling time is the limiting factor in the device's fastest sample rate. If the settling time is 4 microseconds, then the max sample rate is 250 kilosamples per second.

Question two. Calculate the update time of this SPI interface. Feel free to pause the video to give yourself more time. The answer is 2.355 microseconds. Using the formula we defined earlier, we can calculate the critical timing from the values provided in this timing specification table in the data sheet.

Question three. In order from shortest amount of time to longest amount of time, sort the different periods of a DAC update transition. Feel free to pause the video to give yourself more time. The answer is D, but B is also acceptable. The shortest period of time is most often dead time, as it is mostly digital propagation delay. The next shortest is usually the slew period, or the recovery period.

On devices that have very small capacitive loads, the recovery period may be very short, as well. On nearly all DACs, the final settling period is the longest.

That concludes this TI Precision Lab about settling time and update rate. Please find more precision DAC technical resources and search precision DAC products by visiting ti.com/pdac. Thanks.

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