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Hello, and welcome to the TI Precision Labs series on analog multiplexers. This video will provide an introduction to latch-up immunity found in analog switches and multiplexers. The goal of this video is to learn the basics of latch-up condition and its implications to your end equipment.

Here, you can see a typical seamless structure with its NMOS and PMOS gates. As the parasitic PNP structure between VDD and ground start to conduct leakage current, it can enable a secondary parallel and PN structure. This combined PNPN structure, also known as silicon-controlled rectifier, or SCR, creates a positive feedback loop. This can lead to the destruction of the IC due to overcurrent. The only way to halt this feedback loop is to reset the power.

To prevent a latch-up from forming, the p-epi and n-well are placed on top of a buried oxide layer, which acts as an insulator from the bottom substrate. In addition, a trench oxide isolates the NMOS region from the PMOS region. Thanks to these installation layers, no parasitic SCR between VDD and ground can be formed. Ultimately, this will protect the device from latch-up due to leakage currents, as well as latch-up events due to current injection or overvoltage events.

Thank you for watching the TI Precision Labs video on latch-up immunity. To find more switches, and multiplexers, technical, resources, and search products, visit ti.com/switches.