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Welcome to the "T Minus 60" series of videos. In this video, we will briefly go over common tips for creating a layout of a buck converter.

Looking at a synchronous buck converter, there are two noisy loops that are created by high switching currents. One loop is created during the on time of the converter, T1. The other loop is created during the off time of the converter, T2. It is important to keep the loops as small as possible to avoid high losses in noise that will be created by the switching of the converter.

On the right is a simplified version of the TPS7H4001-SP [? EVM ?] layout, which is a space-grade buck converter. The previous device is shown in a real-world example. Each high-current path is kept as small as possible, making sure to keep capacitors close to the device. This allows for the minimum amount of switching noise to be created and avoids unneeded parasitics from causing issues.

Certain pins on a device are more sensitive than others. So continuing on with the TPS7H4001-SP as an example, we can see the sensitivity of different types of pins. Noise-generating pins are almost always power pins, and that is shown in the pins labeled on the right. The power ground, power voltage input, and power output are all noise generators on the TPS7H4001-SP. These are the pins that will create the most switching noise in the circuit. And thus, sensitive signals should avoid traveling close to these.

Less sensitive pins, while not noise immune, are less likely to be affected than other pins, as they are not part of this sensitive control loop of the converter or provide power rails for any analog circuitry. They are often less sensitive because they either stay at steady voltages for most of the time or are used to create current mirrors internal to the device.

There are, of course, very sensitive signals that are either part of the control loop, the reference voltage, or provide power for the analog circuitry that are labeled on the right. Very sensitive signals should be as short as possible and stay away from noise generators or any other noisy signals that may come from other parts of the board.

One piece of advice that will often help out when creating layouts for [? FPGAs ?] is that they will often have positive sense lines that the top of the feedback resistor divider can connect to. This allows the device to offset many of the parasitics that can happen from long output power rails. This can be expanded for situations where the device the rail is powering is very far away. Routing the top of the [? resist ?] [? divider ?] to the positive rail of the device can be beneficial, but care has to be taken to avoid any noisy regions, of the layout as it is a sensitive signal.

In summary, making sure high-current parts are small is necessary for proper layout, as well as taking special care of sensitive signals and the relation to the noise-generating pins.

This video is part of a series