What is clock and data recovery?
Retimers are a key building block in communication systems involving high-speed data transmission. The use of clock and data recovery, or CDR, provides improved clock and data synchronization and also reduces timing uncertainty. In addition, CDRs are valuable as a means of jitter mitigation for a variety of applications. In this video, we’re going to discuss the clock and data recovery function and key metrics used to evaluate a CDR in retimer products.
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Hello, and welcome to TI Precision Labs. In this module, we're going to discuss the clock and data recovery function, or CDR, used in retimer products. Retimers are a key building block in communication systems involving high speed data transmission. The use of CDRs provides improved clock and data synchronization and also reduces timing uncertainty. In addition, CDRs are valuable as a means of jitter mitigation for a variety of applications.
Let's talk about the role Clock and Data Recovery, or CDR, retimers play in real systems. The example shown here is an enterprise switch such as those used in wired local area networks. As data signals are transmitted from one ASIC to another, jitter may arise from different sources. Jitter sources in a system include the insertion loss from the board traces, signal reflections at the connector interfaces, and crosstalk noise from the adjacent signals. Jitter acts as a bottleneck to system speed and performance, limiting the link reach and achievable bit error rate.
A system such as this enterprise switch may use multiple CDRs to restore signal integrity at different points along the data path. Systems typically target performance to industry standards at each of these single points. Retimers are often required to meet those specifications.
What function do CDRs perform in retimers? The retimer uses its CDR to sense the input data and produce a periodic and synchronized clock. This clock, recovered from the data, is then used by a sampler decision circuit. The sampler outputs a 1 or a 0, depending on its input voltage level, and its sampling of the input data is clocked by the CDR. This retiming function using a clean recovered clock allows the output to reproduce the input data but with much less jitter. The retimer thus allows the system to reset the jitter budget for a given data link.
To illustrate the benefit of CDR function, let's examine the output of a 10 gigabits per second retimer when its CDR is enabled versus bypassed. The output I diagrams of the retimer shown were measured using a high speed sampling scope. The retimer test point used is the component edge, defined as a measurement taken for a short distance from its output pins. The total jitter values correspond to an error probability level of one! 1e to the negative 12.
As evident when comparing the two retimer output I diagrams, the use of the CDR reduced to the total jitter by a whopping 45%. Let's examine how a system developer may determine what retimer has the best CDR for their application.
Shown here is a networking system where two ASICs communicate over a backplane channel. The backplane will usually have very long PCB traces, thus the signal will be subject to large insertion loss, resulting in high jitter. In addition, launching the signal across backplane connectors will bring with it some jitter from reflections as well as crosstalk noise. A good retimer is able to handle a very jitter-stressed input signal, such as this backplane case, and still operate error free. A good retimer timer will also output low jitter to the downstream ASIC receiver.
In terms of CDR lock behavior, a system developer will have a list of frequencies that the CDR would need to be able to support. Furthermore, the CDR's ability to achieve and maintain frequency lock in a system will be tested across different operating conditions, including temperature and voltage. In summary, the decision usually comes down to either jitter metrics, i.e. How much did or stress the CDR can handle, and how much jitter propagates to the output.
The CDR in a retimer implements the functional blocks found in a phase locked loop. When the CDR is locked, the VCO output frequency has been pulled to match the input frequency. Moreover, the VCO frequency linearly tracks its control voltage. With the CDR locked, the output data has a strict phase relationship with the input data, and the output voltage tracks phase changes.
Retimer products most commonly implement a type two PLL system, where both phase and frequency detection are used. The CDR lock acquisition for type two is as follows. The initial loop behavior is controlled by the frequency detector. By comparing f out and f in and applying feedback, the frequency delta within the loop is reduced. Once f out minus f in is small enough, the phase detector takes over. The key benefits of phase and frequency detection-based CDR are a wider frequency pull-in range and a faster CDR lock acquisition time.
Jitter transfer is a measure of the CDR output jitter as a function of its input jitter frequency. The jitter transfer is largely determined by the CDR bandwidth, where the bandwidth is commonly specified at the jitter transfer 3-dB cutoff point. The jitter transfer plot can be broken down into three segments based on jitter frequency. Within the stop band, the CDR effectively blocks input jitter from propagating to the output.
Within the attenuation band, the CDR attenuates the jitter from input to output. Finally, within its pass band, the CDR tracks the input periodic jitter, and the input jitter simply passes through the retimer. One additional parameter of interest is the jitter peaking, defined as the increase or boost in jitter transfer at pass band attenuation band cutoff frequency. So the key parameters of interest we have discussed for jitter transfer are CDR loop bandwidth, pass band, attenuation band and stop band, and jitter peaking.
Jitter generation is a measure of the periodic jitter intrinsic to the CDR device. Similar to jitter transfer, the amount of jitter generated as a function of frequency depends on the CDR loop bandwidth. Jitter generation is driven by intrinsic noise parameters such as thermal noise, BJT noise, or MOSFET flicker noise. The purple trace on the current plot illustrates what a typical jitter generation plot looks like. As shown in the plot, the CDR total output jitter is equal to the jitter transfer plus the jitter generated.
Jitter tolerance limits are most often prescribed via networking industry standard such as ethernet and PCI express. A jitter tolerance test involves applying some form of periodic jitter to the CDR are under test and then evaluating its bit error rate performance. Jitter tolerance is often specified as a mass requirement as a function of frequency in terms of UI or Unit Interval. As shown in the illustration on the left, the jitter tolerance amplitude, J1, J2, et cetera, required for the CDR will depend on the jitter frequency, F1, F2, et cetera.
Systems will also require that the CDR be able to tolerate additional forms of jitter. The figure on the right is a screen capture from a pattern generator instrument showing a bit error rate equal to 0, which we all like to see. This test setup has a jitter stress function, allowing the user to apply different jitter types to the signal when testing jitter tolerance. And clearly, the higher the CDR JTOL, the more margin that is available to the system for meeting specification limits and getting us closer to that 0 bit error rate.
Temperature Lock Range, or TLR, is the operating temperature range for which CDR can reliably maintain lock. TLR testing verifies the worst case temperature delta that can be withstood by the CDR while maintaining lock. TLR testing verifies the worst case temperature delta that can be withstood by the CDR while maintaining lock. A large TLR is a signature of a more robust and versatile retimer.
Here we have a diagram illustrating the CDR VCO frequency linear relationship with control voltage. As the operating temperature changes, the VCO plot will shift upwards if cooled down, or downwards when heated up. The CDR by design has an allowable range for its VCO control voltage, to C control min to V control max, per this figure.
An optimal CDR has a control voltage window that allows its VCO frequency to remain locked to the input data during normal operation. In addition, the CDR will be able to keep the VCO frequency locked, even if the temperature ranges from one temperature extreme to the other. A wide TLR is a very attractive feature. A good TLR means that the retimer can be used for a wide variety of application environments.
Now that you know the details on clock and data recovery circuit for retimers, maybe you would like to investigate the other functionality and features that can enhance the performance of your system use case, such as equalization or system diagnostics. Please check for new content on Precision Labs covering these topics.
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Precision labs series: Signal conditioning
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