Welcome to the High Voltage Seminar. This is the PCB layout guidelines to optimize power supply performance session, being presented by Ben Genereaux. My name is Amy Thomas, and I'll be the moderator for this session.

All of the participants are muted for this session, so please use that chat function on the bottom right-hand side of your screen to ask a questions. And be sure to address it to everyone. We'll be answering questions throughout the webinar, and then also at the end. Also, chat if you are having any problems hearing or seeing the presentation. With that, I'll hand it off to Ben to get started.

Thank you, Amy. Like Amy said, my name is Ben Genereaux. And I'll be presenting on PCB guidelines to optimize power supply performance. So let's get started.

So first off, what should you expect to get out of this session? So we'll be going over the fundamental concepts needed for a successful PCB layout as it applies to switched-mode power supplies. And the concepts that we were talking about today are applicable to all power supplies, regardless of power level.

So we'll be talking about a few of our parts, and I'll just reference these throughout presentation. But just so you know, our UCC28180 is our continuous conduction mode. Our factor correction controller, UC28742 and 10, are the fly-back controllers. UCC24612 and 10 are synchronous replication controllers.

So why is layout important? Number 1, it's how you'll be bringing your design into the real world. So you might have a perfectly great schematic and design. But if you don't have a functional layout, you're going to have a bad time debugging and getting your design to work.

So essentially what we'll talk about is how it translates schematic into working hardware and get physical hardware that works in the real world. And the layout can be extremely complicated. There is a lot of parasitics to understand and deal with when you actually design a physical layout.

So our agenda for today, just to outline it, we'll take a look at a schematic and then talk through the parasitics that we are concerned with. So that is resistance, inductance, capacitance. We'll also talk about EMI safety, some grounding and signal routing tips, thermal management, and finally walked through a small example.

So first. Our primary concerns with a layout for power supplies-- safety, EMI, parasitic inductance, capacitance, resistance, thermal performance, high dv/dt switching voltages, high di/dt switching currents, how we do our grounding, and then noise mitigation throughout the design. So we want to be aware of all these areas on our PCB.

So before you begin a layout, you're going to have to have a schematic. So you probably, at this point, finalize the schematic. And you need to get started with your layout. It's important to first have a strong understanding of the circuit and that helps to start with a clean schematic. And it also helps to group together components that might appear together on the layout, so you have them together on the schematic. That can make things a little bit easier.

So, we want to have a strong understanding of the circuit. And so that includes the parasitic components that we'll talk about today. So if we think about the concerns that I just mentioned, we want to identify where these are before beginning the layout. It helps to plan ahead of time.

So for example, you have our high our paths, our high dt/dt, or our switching currents and where these high current loops. High dv/dt regions, so that would be our switched node.

We're going to want to understand the thermals. So you should understand and calculate losses through your components and understand, can we dissipate heat to the PCB, or maybe only to heat syncs on the board.

Also, yes, safety-- so understanding what standards we're designing for and how that affects our layout. We also want to optimize the design for EMI performance. So pay attention to how we route the EMI filter. And then grounding-- finally, it's important to understand how we're grounding our design, with the power grounds and analog ground sections.

So once we understand the schematic, we can start thinking about power actual layout. So getting started with understanding parasitics in the circuit. Start with resistance. And with our component selection for sets or inductors, for example, we typically understand the resistances as we're respecting our components and selecting them.

And we understand the impact that those have on efficiency and regulation. We don't always think about the copper traces. They will have some resistance. And that helps because the impact in our design, or regulation, efficiency, which leads to temperature rise for excessive losses.

So the calculation for resistance of an inductor is related to the resistivity of the conductor and the physical dimensions that we show a table here with some common conductors used in PCB design.

So if you think about copper, which will be in our traces and route. Throughout the PCB, this is the one we'll all focus on. And so just by looking at the formula, since we're proportional to the length and inversely proportional to the cross-sectional area, this tells us short, wide traces are going to have the lowest resistance. So something to think about there.

And we also want to note that temperature has an impact on the resistivity of metals. So for example, looking at copper in a 100 degree Celsius temperature rise, you might expect a 40% increase in the resistivity. So something to keep in mind also.

So a good method to estimate parasitic resistance is the method of counting squares. So if we break down our formula for the dimensions of a square inductor, we can cancel out both lengths here. And so our only variables are the resistivity and thickness.

So this simplifies things quite a bit. We don't have to calculate the formula every single time. We're calculating the resistance, and we'll see some estimations here for different copper weights. So for example, 1 ounce copper has a 1.4 mil thickness. And that gives us about 0.5 milliamps per square.

So looking at an example, we can look at the resistance of these traces connected to a thermosense resistor. And so we see two squares in series here. So add up 0.5, 0.5, that gives us 1 milliamp.

And then, for example, I want two squares in parallel. So we have half the resistance, so 0.25 milliamps. So it doesn't matter how big squares are or anything, it's just a rough estimation based on the length canceling in the formula.

So this is a quick method to use. You don't want to be spending a lot of time on calculations for every single trace in your circuits. And you'll see at higher currents this is where this really makes a difference.

So let's not forget about vias. Vias also have resistance. And so sometimes we forget about the vertical path to the board. And so we can rearrange our resistance formula for the cylindrical geometry.

And so, given this example, with these dimensions here, we plug those numbers in, and it comes out to 0.67 milliamps, which, as I mentioned before, you get to higher currents. Maybe 10 amps there would come out to 67 milliwatts loss. So that can make a difference in a power supply with either regulation or efficiency.

And so with higher currents, you're going to want either more vias or larger vias. So a typical rule of thumb is I consider is 1 amp to 3 amps per via. So it doesn't hurt to add more vias. If you have the space, it'll improve your design performance.

So let's look at an example here and apply this counting squares method. So you can see here we have, for example, layout to the dual output filters. So we've got inductor and capacitors. And this red trace here is our output, so pulling out of the inductor into our output connector here.

And then in blue you can see, so this would be our voltage sense trace going back to the controller and feedback network. So if we're sensing our output voltage at the inductor here, there's going to be some drop in the copper between the inductor and the connector.

So if we think about maybe one square here, one square here, another square could be here, and then plus we have the output connector. So maybe it's two or three squares for 1 ounce copper. That would be 1 milliamp to 1.5 milliamps. And so 10 amps, it comes out to about 10 to 15 millivolts of drop in your voltage. So that will definitely impact your regulation, because you're sensing not at the output connector.

So to improve that, let's take a look here. We're now sensing at the output connector. So you'll have much tighter regulation by sensing here. And so that is the recommended method to avoid that drop due to the parasitic resistance.

All right, so another type of parasitic that we are concerned with is inductance. And so that causes an issue in our high di/dt loops. And it's also known as our switched current loops.

So we simplified the schematic that I showed earlier. It's a continuous conduction mode, R factor correction boost. And so we have this diagram here to represent that.

The issue with having parasitic inductance is in high di/dt regions is it will cause voltage spikes. So you may have seen this before on your switched node. You'll have a high voltage spike, quite higher than the expected max voltage on the switched node.

So this will cause issues with EMI performance and coupling to other nodes. And it's causing general circuit malfunctions with voltage spikes occurring on the board. So that's really why we want to identify and understand our circuit and what regions we need to be mindful of.

So let's take a look at these loops that we've highlighted here. So this current loop in green, which show our inductor current, so this is relatively low di/dt compared to the rest of the circuit. So the stray inductance, parasitic inductance is less of a problem in this loop.

And if you think about it, you put a inductance in series with our large PFC inductor here, it's not going to make as much of a difference as in the other loops. So if we look at the output loop, we highlight two loops here in blue. The path is set. So we show our current in this diagram here. This is high di/dt because, as I said, it's turning on and off.

And then complementary to that, we have our diode current. So turns that off time. We have current flowing through the diode, forms this in red here. So these are high di/dt regions that would be susceptible to issues when we have significant amount of inductance

And so we really want to minimize the inductance in this loop. So we can do that through a layout, by forming a tight loop between these components so that we're not generating a lot of parasitic inductance leading to voltage spikes.

So another source of high di/dt is reverse recovery. And we'll see this in CCM topologies. So as current is flowing through the output inductor, output diode, and the set turns on, our current will reverse directions here. And by pulling charge out of the junction of the diode, you can see this current waveform. We get we get a di/dt high spike right there. So not ideal for our circuit performance.

So like I said, if we can minimize this loop here, keep it as tight as possible, we can mitigate some of the effects of the high di/dt. Yes, so we're minimizing the loop. And then another idea to keep in mind is that we want to use low QRR rectifiers, so minimize the reverse recovery recharge inside the diodes. We can minimize this voltage spike.

So that means for a high output voltage design, like a PFC boost, we're boosting up to 90 volts. We want to use silicon carbide. And then for most other designs, that either means the Schottky or ultra-fast diode. And if we are using synchronous rectification, minimize the reverse recovery method.

So yes, the next area that we have to watch out for was high di/dt, the gate drive loop. So adding on to this PFC boost example, showing here the square gig drive voltage signal. And as we're turning on and off, we're charging and discharging the gate capacitance.

So we can have some high current spikes. As you can see in this little diagram here, that current is in this loop highlighting yellow. So again, we want to minimize this loop, minimize the inductance.

So we have a nice, tight loop. And that can prevent any limitations to our drive current to prevents ringing on the gate drive signal. And that's something that you really want to avoid. Any ringing on the gate drive signal could possibly cause a false turn-on and be disastrous for your circuit.

So minimize the loop inductance here in high di/dt region. And then in blue, this switching region is a high dv/dt region, which can couple to noise-sensitive circuits. So we'll talk a little bit later on about minimizing capacitance and how that impacts your layout.

So now let's talk about the digital source of this parasitic inductance and how you can calculate and estimate what you might see in your design. So the equation we showed here are empirical. They're good tools to estimate the inductance of a free conductor in space.

So if we look through this, we can generate a rule of thumb. We think we typically say six nanohenrys per centimeter based on common PCB trace with some 1 ounce copper. So you'll see with just a free-floating conductor, the natural log relationship limits what control you have over the inductance.

So what we'd want to do to minimize the parasitic inductance helps to have a ground plan under or over the traces. So it creates a return path that's very low inductance. And again, these are empirical calculations here. So we want to be aware of that so that these give you meaningful results, you typically need a high ratio of the length to height, so this separation between the ground plane and your conductor.

But I think that's pretty common. So for PCB, we just have our insulator or FR4, or whatever, very thin compared to the horizontal dimensions of your copper on the PCB. And so you'll see with the modified equation, accounting for a ground plane, we have it control with direct relationships between the height, the length, the width, over inductance.

And just some quick calculations here. So we originally said it was about 6 nanohenrys per centimeter for 1 ounce copper. And if we keep our width to about 2.5 centimeters, we'll see about 1.2 nanohenrys, quite a bit lower than 6 nanohenrys. And it makes a difference throughout the whole layout design.

So we'll take a look at an example here and try to apply this, so similar to our output filter to what we looked at with parasitic resistance. And what we're going to look at here is how much inductance is in series with T39. So that 2 centimeter length that I highlight here, so that's between the inductor and this capacitor.

So if we say that's 2 centimeters, 2 centimeters times 6 nanohenrys per centimeters will give us 12 nanohenrys parasitic inductance. So this length here is something that we'd want to minimize. And we're forming like a larger loop by extending our topper all the way out to the side here.

Something that makes more sense and would lower our series inductance is placing this capacitor right next to the inductor. So you'd have a nice, tight switching current loop there.

So the next parasitic that we'll talk about is capacitance. So parasitic capacitance will cause issues in high dv/dt regions. And so that's typically on switched nodes. So you see our switched node here, it's where our voltage is switching between 0 and the output voltage.

And so all switched node power supplies will have at least one switched node where we need to be aware of this performance. So this has been highlighted in blue on our PFC boost example. Again, where we need to pay attention to this.

And issues that can arise are EMI problems, so noise coupling to other circuits and reduced efficiency. So if you're inducing voltages and currents on other circuits, you'll have stray currents that will reduce your efficiency.

How can we mitigate this? First off, minimize the switched node area. So if you want to keep this region in blue to a minimum amount of copper area on our PCB, it's less likely to couple to other nodes and radiate this high switching voltage around.

Also, we'd like to keep the sensitive etches away from the switched node. Further away the sensitive traces are, the lower the parasitic capacitance will be less likely that it have noise coupling from the switched node. And another tip that we'd like to use-- grounding the heatsink. So pretty common to have a heatsink on your set here or diode.

And if you have a heatsink grounded, any voltages coupling to it would be shunted straight back to ground instead of radiating throughout your power supply. So it forms like a shield there.

And then one thing you might be thinking is if we're lowering our trace with an area here, we're sacrificing resistance and inductance, so better cooling. But by decreasing the surface area, we get lower capacitance. And so creates a paradox there.

But what we'll say for your primary concern here would be to lower the capacitance, so focus on decreasing the surface area. So we can lower resistance and lower inductance, we can shorten our traces and have a very tight switching loop. So we can manage those in other ways.

And coolings-- yes, if you can't dissipate the heat in the PCB, then heatsink might be required. So our primary concern is lowering the capacitance.

All right, so let's talk about how this is physically created. And we show the formula for capacitance. And if we can assume 5 is our estimate for relative permittivity for our PCB insulator, so we'll use 5 here. And that's pretty common throughout PCB manufacturing.

So then the permittivity of free space is constant. So we only have the area and the thickness to worry about here. So in this example, if we have two 10 mil traces crossing each other perpendicularly-- so some through here, through here-- this is our region we need to calculate capacitance for. So plugging in those numbers, you come out to about 0.01 picofarads.

So that's very small. So two traces crossing perpendicularly aren't making a huge impact on the parasitic capacitance here. You might have traces crisscrossing throughout your board.

But what we really need to watch out for are the planes and parallel traces, and then large component pads. Those will be more significant culprits that where our parasitic capacitance is coming from. Like I said, not much capacitance here. But you look throughout an entire circuit, you'll have a lot of overlap of copper throughout your PCB.

So let's take a look at a schematic here. This is a flyback example. So in a flyback, you'll have two switched nodes, one of the primary side right here at the train of your FETs. And then we highlight the other one here in red. This is at the train of our synchronous rectifier.

So this is a high dv/t region, which means we need to be mindful of parasitic capacitance. So we also highlight in green our noise-sensitive feedback network, so very important for the regulation and performance of our power supply.

We'll want to avoid significant parasitic capacitance between this and your switched node. So we really can't have this region underneath our switched node. That would be coupling a lot of noise. And if we maybe estimate 10 component pads, so some component pads from this region, we calculate that area and we can increase the parasitic capacitance to 2 picofarads, which could significantly impact this very noise-sensitive region.

All right, so let's talk a little bit about parasitic capacitance and common mode inductors or common node chokes. So the common node choke is used in EMI filters. And if you look at this graph here, you typically see this in the data sheet for one of these components.

And what we want to highlight here is how as the frequency rises, the impedance drops. And so the impedance drops at our inductor, essentially turns into a capacitor. And at high frequencies, the intertwining capacitance of the inductor-- that's where that impact comes from.

And so we look at an example here where we place a ground plane underneath our common node choke. For example, a 3 centimeter square ground plane with this thickness, a one layer circuit board, we'd calculate two regions of 50 picofarad parasitic capacitance.

So adding this in, the parasitic capacitance already exists. This is not ideal for EMI performance. We're creating paths that high frequency signals can travel on and couple to and the ground plane this very low impedance. So we really don't want to place one of these under our EMI filter.

So continuing with the discussion on EMI, I'll discuss a little bit about magnetic coupling. And this is something to keep in mind. When placing your inductors and designing a EMI filter, the magnetic field, so I can couple between inductors, inducing currents, and creating your EMI performance.

So a couple of ideas that we have to mitigate this is changing the orientation of your inductor so that it's not as susceptible to coupling. And then experiment with different core shapes or looking to different core shapes that are optimized for EMI and provide better shielding. Or you can provide a physical shield in your circuit, something that would block the magnetic coupling.

And so a few more tips on EMI considerations. We've got a sample input filter layout here, the CRAC connector. We want to place components away from noise sources. So we want to filter away from the noise sources.

Like we talked about, less chance of coupling. We don't want to cross the input and output traces of our common mode choke-- for example, T2. We talked about no ground plane under the filter. And then so lower resistance means wide, short traces. And we want to be mindful of our high voltage safety requirements to find our spacing between our traces.

So we just mentioned safety. If you look at the diagram here, our primary concern with safety is keeping hazards, voltages away from user-accessible points. So you need to understand what standards you're designing for.

And they'll typically tell you the clearance and creepage that you need to maintain. So we've got an example table here just listing some clearances for various isolation levels, some sort of functional basic reinforced.

And then the diagram shows a couple tips for increasing those clearances and creepages in your slot and your PCB or physical barrier. And like I said, this depends on what standard you're designing for. So it depends on type of insulation, pollution degree, your AC voltage, and working voltage.

So talked about some ground planes now and how this is important in your circuit. So we already talked about resistance and inductance a little bit. So with resistance-wide paths are lower resistance. And placing a ground plane underneath the trace will lower the inductance and provide a return path for any signals.

The other thing is that we will improve our thermal performance with ground planes. So it can spread heat across the board.

And consider flooding-- any empty areas on your PCB with ground planes. Here we're showing the ground plane underneath our controller and accompanying resistors and capacitors.

So this helps in a couple of ways. We said heat. Also, you want the shortest return path for ground through the loops in your circuit. So it also helps place several vias and have ground on multiple layers. And if you have a multi-layer PCB, you can typically get a pretty solid ground plane underneath your controller.

And talking a little bit about small signal routing, we want to avoid coupling to sensitive nodes. So our parasitic capacitance comes into play. And you can see the difference between our bad and our good example.

We have our current sense resistor. And then we're filtering it with a cap and resistor. This is a very sensitive signal. So any noise coming to it from the switched node is going to hurt our performance. So we want our filtering components as close as possible to PIC. And we want to be as far as possible from the switched node high dv/dt region.

Also, we highlight here-- it helps to place ground vias near caps and resistors in the IC. So if you have a via near this capacitor, we'll have a very short return path to ground of our IC.

Another tip on signal routing and placement, you'll see in all the data sheets, like TI parts zone. A lot of recommendations on the layout, so always helps to read that when starting a layout. And then oftentimes, the pin-out of their controllers are optimized for good layout. So you can see on this one, we're separating analog and power plane.

So moving on to thermal management. You're going to want to understand how heat flows throughout your system. And so it helps with your PCB cooling strategy,

Solid ground planes, like we said, definitely good for an optimal design, and avoiding breaks in those ground planes so you can spread as much heat laterally as possible.

So if we want to get heat onto different layers, we should use vias. So you can see in this example here, we're using vias to get the heat to our outer layer on the bottom of the board here from our IC. So then we have a large area on the bottom layer where the convection radiation will spread that heat out quite a bit.

And then, again, do not use the switched node for cooling. If we're assigning a very big switched node, we're going to have some noise issues.

So an example here, why is board A hotter than board B. You can see, board A here, the IC's hotter. The bottoms of the board's hotter. And then board B, we've got a diode that's 66 degrees C. And the bottoms of the board's cooler, so pretty clear.

In the top example, there's something, a trace here preventing this ground plane from spreading the heat out across the whole board, causing our controller to heat up quite a bit. And so we spread the heat out, and we get our controller down to a more reasonable temperature.

So let's walk through an example here. So the first step before beginning your layout, you'll have finished your schematic. And like we said, you really want to understand that schematic and where these major issues that we've talked about, where these parasitics are, and how they play into the performance of your circuit.

So besides that, there's some other stuff you should know-- limitations of the system that you're actually putting this PCB into. So to find your size, how many layers you can have on your PCB, input and output connections, mechanical restraints, manufacturing constraints, can you use components on both the top and bottom of the board, can you just put two holes on one side of the board.

And then creepage and clearance requirements-- that's related to safety. So you need to understand what safety standards you're designing for.

And then, like I said, understanding the circuit, we've identified these areas and how to mitigate the problems created by them. So we say, use this trunk-packing algorithm, which means placing your large power components first. So for example, this is a PSR flyback using synchronous rectification.

Our large components are a transformer, FETs, capacitors. That's what we want to place first and build out to our power path. So you'll place your large components, and then finish placing the power components.

The next step would be to place your controller. So we show here placing the SR controller and then our flyback controller. And quiet corners of the board here, we don't want them in the power path. We want them farther away from switching voltages. So reserve a quiet location for the controller.

And then after you decide where to place your controller, you can place associated parts nearby, so probably resistors and capacitors close to the pins, both our SR controller, flyback controller.

And so this is an iterative process. As you place more components, different orientations might make sense. And so it did take some time. We went through a couple iterations and figured out what makes the most sense.

So now looking at routing in our example, we've got red on the bottom layer and blue on the top layer. So we want to route our power path first. And in our power path, that means short, wide traces, minimizing the resistance and inductance in those traces.

You also want to minimize high di/dt loop area, which we show in these yellow and red loops here. Our input loop passing through the capacitor to transformer to set ground. We have a nice, tight loop here, about as good as you can get it.

Same for the output loop. We're going to the transformer to diode to capacitor back to ground. And we've also got the nice tight loop here, minimizing our parasitic inductance.

And similarly, we want to minimize the high dv/dt area. If that occurs on the diode and the FET, so we've got about the size of the pad on the diode here and our FET switching voltages in this trace here. So this would look good for real-time.

So after the power paths, we'll route the signal traces, keeping in mind, keeping away from the high dv/dt areas. And ideally, noise-sensitive traces will be short and have short returns paths, so plenty of vias and good ground return paths to the IC.

Finally, we will place our ground planes. So flooding empty areas with ground is a good idea. We show where the ideal areas would be on this board-- that's primary ground. So we're connecting to the book cap, and then spreading our primary ground underneath the controller and associated the components.

And then on the secondary side, we have the ground plane under everything on the secondary side. So like I said before, want to use plenty of vias connecting to ground planes. So putting them in your caps and resistors will create short return paths to the controller.

And then trying to keep the nice, clean, ground plane to spread heat. And it makes sense. So be mindful of traces cutting through the ground plane and blocking connections.

So then to wrap up, summary-- understand your circuit. So where the high current, high di/dt, high dv/dt. And so we now know how that impacts our parasitic resistance, inductance, and capacitance.

We talked a little about EMI safety requirements and thermals and some tips for managing those. And then so based on the layout example that we just talked about, always place large components in the power path, and small parts, power routing, signal routing, and then placing our power planes.

So finally, you want to have someone review your layout. It always helps to get a second set of eyes on it. And definitely custom review it before sending it out for fab.

And then support for your reference. We take a look later at this presentation. I've got some references here that were used to make this presentation. And then they go deeper into layout tips.

All right, thank you for listening to my presentation. I think now we will have some questions.

Ben, thank you. We do have a couple of questions I think we have time to get to. And the first is, should a void be placed under the switched node on the inner ground plane?

Should a void?

Should a void be placed under the switched node on the inner ground plane?

OK. So yeah, on this example here, you can see how we have our ground plane separated from the switched node. So our switched node trace is in this point and this point. So having the ground plane directly underneath it, probably not the best idea and could couple noise to the ground plane.

But I'd say it'd be more important to separate other sensitives, traces from the switched node. But I think something like this makes sense. You're not overlapping the ground plane in the switched node, I think, if I understand the question correctly.

This next question I think is similar, Ben, but I'll ask it just to make sure. What are your thoughts on setting ground planes underneath the switching inductor.

OK. Yeah, similar question. So if you can avoid it, probably better. But at the same time, I think I've seen designs where they do that, where they place the ground plane completely flooding the area because the ground plane won't be susceptible to the noise. But I would say in general the best practice would be to avoid it.

It looks like we have a third around the same topic, but I'll ask since we're on the slide. What are the trade-offs between flooding, the empty areas of ground planes, and increasing the parasitic capacitance?

OK. so the ground plane is a very quiet region. So having the ground plane flooded underneath our controller and all of these sensitive analog nodes, that's not an issue with the parasitic capacitance that we're really worried about. The issue would be the size of the noise her, like the switching nodes. That's where parasitic capacitance becomes a large issue.

So I don't see much of an issue with flooding the ground plane. But the overlap, you don't want a ton of overlap under the high dv/dt regions. That's where that parasitic capacitance is a major problem.

Is there a typical or recommended layout for high voltage T0220 half-bridge?

If that's a TI part, then there probably is. I'd have to look up that part and see what it actually is. But we might have some designs published online with it or the data sheet will go through optimal layout, but I'm not familiar with that part.

How would you route the analog digital ground of a microcontroller and the power ground?

That's a bit hard for me to answer. I haven't done much mixed signal design. So I would have to leave that to an expert on digital power. So maybe we can look into that and get back on that question.

Any considerations for LDOs connected after switching regulators?

Yes. With the LDOs, you probably want the shortest connections from the output of our switching regulator to the input of the LDO. I know you can minimize the input capacitance required if you have a shorter trace there.

But I guess similar to what we talked about to, try to keep the LDO away from high dv/dt regions in the switched mode power supply.

It looks like we got a clarification. It wasn't actually a part, Ben-- it's a package. So it's like a moderator mistake here. So TO-220 package, common through-hole package for FETs. Sorry about that.

Oh, OK. So what was the whole question again? So TO-220 would be similar to this FET here. What's the whole question?

And then the question was, is there a typical or recommended layout for high voltage TO-220 package half-bridge?

OK. I think it depends on your exact design. So this is a half-bridge here. But we see the high voltage switched node net is this pin right here. So that's offset from the date and source. And we're not trying to get the switch node coupling to those pins.

But I don't know if there's a recommended layout. Sometimes people can put them back-to-back on a heatsink or right adjacent next to each other. I think it's more of a case by case basis that I'd have to look at to answer that question.

Parasitics are always present. And when they integrate, they create resonant circuits, series in parallel, a very high frequency. Is there any tool to visualize this?

Can you repeat that one more time.

Sure, no problem. Parasitic are always present. And when they integrate, they create resonant circuits, series in parallel, a very high frequency. Is there any tool to visualize this?

Not that I'm aware of. I think that if you're trying to stimulate the parasitics and everything in a circuit, I guess you typically don't see that like in a typical T spice.

But if you were able to simulate it, it might be interesting to see. Might take a while to simulate. But on the top of my head, I'm not aware of anything. It would be interesting to look and see if there's anything out there that simulates this.

I think the best way, what I talked about today, is these mitigation techniques are the best way to avoid having to calculate every single parasitic. And it's not something that you'd want to spend a ton of time doing, but something we could look into.

This next question that I can answer-- will this presentation be available on TI.com. Absolutely. This recorded presentation, along with all the resources that Ben mentioned in his presentation, will all be linked together. And we'll send that back out to you guys. You can easily find it.

I think you have time for a couple more. Between switched node as GaN LLC and transformer primary guide, what considerations should be considered, WRT-- after that, it stands for something technical, but I don't know the name of, Ben, sorry-- ground coupling and antenna effects, especially is GaN on daughter board and transformer on main board.

OK, can you go through that one more time.

Yes. Between switched node of GaN LLC and transformer primary guide, what considerations should be considered WRT ground coupling and antenna effect, especially if GaN on daughter bought and transformer on main board?

OK. With respect to-- thank you. With respect to is what you were trying to say. Thank you for the clarification.

OK, so I think you might be using TI's GaN daughter card. And so I believe they have some recommended layouts, tips for that. But yes, there's only so much you can do with the daughter card.

So placing it adjacent to your transformer and shortening the switched node as much as possible, and that connection is the best you can do. So there is a bit of sacrifice, I guess, of working with the daughter card. And you're a bit limited when you're not integrating everything under one PCB.

But I think you can still get good performance with the daughter card. And if you still think about the practices that we talked about and just apply that and just assume the daughter part as a component, short switched node traces, you'll get the best performance out of it. I'm not I'm not sure how much like mounting it up vertically. I haven't seen really any major negatives to that.

OK, I think we're out of time, Ben, for this presentation. We didn't quite get to everything. But we will be happy to follow up with you guys later on any other questions you might have.

OK, all right. Thanks, Amy.