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Welcome to TI Precision Labs. In this series, we're going to discuss DisplayPort, or DP link training. DisplayPort has become a standard for connecting PCs, laptops, and other computers to video monitors. It is also available on video graphics cards, docking stations, projectors, and other computer peripherals. Having a solid understanding of the link training mechanism would help in understanding and debugging common design issues associated with the DisplayPort interface. If you have not watched the first part of this series, "What is DisplayPort," please watch that before continuing this video.

For DisplayPort, there are three major components. The main link, the auxiliary, or AUX channel, and the Hot Plug Detect, or HPD. The main link is used for transmission of video and audio. The main link consists of a number of unidirectional serial data channels that operate concurrently. These are commonly referred to as lanes. The AUX channel is a half duplex bi-directional data channel used for control and status information. HPD is a 3.3-volt signal provided by the sink to the source.

Let's start with an overview of the DP connection sequence. The sink starts by driving high on the hot plug detect, indicating to the source that there is a display device connected to it. Once the source detects HPD being high, the source reads the sink Enhanced Extended Display Identification, or EDID, through the AUX bus. The EDID is a data structure that describes the sink capabilities to the source. The source then reads the sink DisplayPort Configuration Data, or DPCD, through the AUX bus. The DPCD is a data structure that describes the sink link and DSC capabilities to the source.

Link training establishes the physical link parameters used for transmission of video and audio over the DP main link. The link training consists of two sequences. The first sequence is the clock recovery. Once the clock recovery sequence is complete, the source will start the channel equalization sequence. Once the link training is complete, and if the video audio content is flagged for content protection, the High-Bandwidth Digital Content Protection, or HDCP, authentication protocol is used. Compressed and encrypted video transmission is then initiated through the main link.

Now let's take a look at the clock recovery sequence of link training. Please note, this is a general representation and may change depending on the specific source and sink implementation. The purpose of clock recovery is for the sink to recover the source clock from the data stream. The phase and frequency of the sink PLL will be synchronized with the data stream during clock recovery.

The source starts to see transmitting the TPS1 data pattern on the main link. The source normally starts signaling with the minimum drive setting, which is voltage swing, pre-emphasis, and post-cursor 2 at level 0. To meet the CR done condition, the sink only sets its CR Done bits and its DPCD register when its linked CDR unit has maintained the frequency lock. The sink must set the CR Done bit for up to four lanes in the DPCD register to complete the CR portion of the link training and move on to the channel equalization sequence of link training.

Once the source transmits the TPS1 pattern, the source will then check via the AUX channel if the source in sink has managed to recover the clock. If the clock has not been recovered, the sink device can request new settings for voltage swing and pre-emphasis to try for the next iteration. The TPS1 will then be transmitted, and the source will again check if the sink has managed to synchronize the reference clocks. This behavior will loop until the pre-emphasis and pre-emphasis and voltage swing have changed up to five times or until the reference clocks have been synchronized.

If changing the voltage swing or pre-emphasis fails to realize the CR lock, then the source can reduce the link rate or lane count and return the link rate to the value used at the beginning of the CR sequence and repeat. If any of the CR Done bits remain unset, even at the reduced bit rate and/or the reduced lane count after all the voltage swing values have been tried, the source ends the training without establishing the link, which typically results in a blank screen.

Once the CR is completed, the source will start the channel equalization sequence of the link training. In the EQ sequence, the source transmits the TPS2, 3, or 4 data pattern on the main link. The source will also use the drive setting and link configuration from the CR phase to start the EQ training.

The source resets the loop count and must wait before reading the linked status bits from the sink DPCD registers through the AUX bus. If the CR Done bits are set, the source will stop transmitting the training pattern to indicate the end of training and then start the transmission of video stream data. If the CR Done bit is not set, then the source needs to downshift to the lower link rate or lane count and return to CR. If the link rate or lane count is already at its lowest, then the source ends the link training, which will result in a blank screen. If the CR Done bit is set and the EQ Done bit is not set, the source needs to read the sink relevant status bits.

Unless all status bits are 1, the source must continue to adjust the drive setting according to the request by the sink unless max drive level has been achieved. The minimum loop count on this sequence is one, while the maximum loop count is five. The loop count is incremented by one on the AUX [INAUDIBLE] when all the relevant status bits are not being set. When any one or more of the status bits are not 1 in the sixth loop, the source needs to downshift to the next lower data rate or lane count and then return to the CR sequence to the CR sequence. If the link rate or lane count is already at minimum, then the source will end link training without establishing the link, which will result in a blank screen.

DisplayPort requires a high-speed interface to support high resolution video. Maintaining signal integrity for these high-speed signals over the transmission media is very important but also quite challenging. A redriver or a retimer placed on the main link between the source and the connector or between the connector and the sink can help alleviate some of the high-speed design limits. For more detail on a signal conditioner, please refer to the TI Precision Labs presentation What is a Signal Conditioner? and What is the Difference Between Linear and Limited Redriver?

Since having a signal conditioner helps to improve the DP main link signal quality, we can use the DP link training to help tune the signal conditioner settings. For example, we can tune up and down the signal conditioner setting until the link training fails. This will establish a lower and upper boundary of the [INAUDIBLE] By choosing a setting in the middle of the boundary, we will then ensure that the signal conditioner has the maximum operating margin. Be sure to visit our E2E support forums at ti.com/e2e, where we can help answer questions about designing with interface technologies. Please also reference previous TIPL videos like our video on I diagrams.