[AUDIO LOGO]

Hello, and welcome to TI Precision Labs on Embedded RAM Memory. In this video, I'll discuss how RAM is used in an embedded system, key terminology for RAM, and how RAM compares to flash. Let's get started.

This is a very simple example of a processor or microcontroller and its internal connections. While there may be many instances of the blocks you see here, all processors and microcontrollers will have at least one of the following; the CPU, or Central Processing Unit responsible for the main operation of the device, peripherals that are controlled by the CPU, these can be anything from communications peripherals, such as SPI or UART, to embedded analog blocks such as ADCs, DACs, or actuation peripherals such as PWMs.

Finally, there must be some type of memory that stores the data for the device to use. The basic role of the memory in an embedded system is to either contain program code that the CPU will execute or to store data variables for both the CPU and peripherals. Memory can be either internal to the device or externally accessed through the device's pins.

We can further classify the memory by how it behaves when the device does not have power. For volatile memory, the memory contents are lost when the device has no power. There are some devices that have low-powered modes which maintain RAM, but check your device's documentation to verify the details. For nonvolatile memory, the memory contents are preserved when the device has no power. Some examples of volatile memory are SRAM, DRAM, and caches. Some examples of nonvolatile memory are flash, FRAM, and ROM. Today, I will be going more in depth on RAM.

Now, the device memory needs a way to transfer data to other areas of the device. This is accomplished with the memory bus, parallel set of connections that enable the main memory to interface with the CPU, I/O, and other peripherals through a memory controller. This bus is restricted to a specific width or data size, which is dependent on the device itself.

The bus can be multiplexed, such that a peripheral or CPU can determine when to read or write data to the bus without reading or writing at the same time as another peripheral on the bus. The diagram of the memory bus shown here is a conceptual representation of how the components connect to memory and will vary in its structure amongst different devices. Check the device data sheet to find out how the memory bus is configured.

At this point, you may be asking why one type of memory is used versus another. Let's take a look at some typical trade-offs between volatile memory, in this case I will consider SRAM, and non-volatile memory, and I will use flash as the example for that category. To reemphasize, the biggest difference is one we just talked about. an SRAM will lose its contents between power cycles while a flash memory will retain those values.

Next, are some not so obvious differences. Due to its physical construction, SRAM can usually operate at the full speed of the CPU of the device. This would mean that its access time is the same as the clock rate of the device. On the other hand, flash memory typically cannot run at the full speed of the CPU of the device. This would mean that its access time is slower than the clock rate of the device. These statements are not absolutes, so be sure to check the device data sheet for your device to understand the behavior of all memories.

Again, due to the physical construction of the memories, SRAM and flash handle reads and writes very differently. SRAM behaves in a manner, that I would say, is the assumed normal for a memory, in that the CPU can read and write to the SRAM through basic and direct instructions. Flash, however, can only be directly read by the CPU and requires special operations by the CPU to write new data.

Finally, flash memory introduces the concept of endurance or how many times the contents of the memory can be changed over the lifetime of a device. SRAM does not have this restriction, so it is something important to understand for your end application.

The first image shows the allocation of data on RAM compared to flash. This diagram is based on the F280039C device. As you can see for flash, the tables and code are stored in various sectors of a single bank. Whereas, RAM needs to store the items over multiple RAM units. On a device that is run from RAM, things that will be needed to run the program, such as the code, variables, and other quick-access items are loaded to RAM. It is worth noting that code can be allocated to RAM by copying it from the flash where it was loaded, and then running from the RAM address. This would enable the device to run standalone if power cycles.

The next image is source code from a Linker command file for the F280039C device. The Linker will use these instructions to define various memory locations such as flash, RAM, and ROM. The linker also allocates items to different memory locations, either in RAM or flash. You can see here that the various code sections, data spaces, and tables are allocated to different local RAM spaces. If upon building your program you find that there is not enough RAM in the device, you may need to either optimize your code or change to a device with more memory available.

Let's go over some basic memory terminology that will be necessary as I explain in more detail how the RAM can be accessed. The smallest data grouping in any memory is referred to as a bit and is simply either a binary value of 0 or 1. Bits are notated with a lowercase b. So if I want to show the value of 10 kilobits, that would be notated with a 10 followed by an uppercase K and lowercase b. Note, that in this terminology, the letter K is capitalized as it refers to 2 to the power of 10, or 1,024 units, and not simply 1,000.

The next representation is the byte, which is a grouping of 8 bits. Bytes are notated by an uppercase B, So 10 kilobytes would be written as 10 KB. This is a very typical size notation since many embedded devices are 8-bit or byte addressable. Next, is the word notation. The length of a word can vary depending on the CPU architecture in your embedded system. A word may be 16 bits, 32 bits, or more. This is notated by an uppercase W, so 10 kilo words would be written as 10 KW.

Next is the long notation. This is simply the next largest integer allocation above a word. Typically, this is a 32-bit number but can vary depending on your target device. The floating point notation is the same as the long but contains decimal values and can represent much larger values. Finally, there is the double, which is a 64-bit number that represents decimal values and contains more precision with the larger range than the float.

To assist in debugging, Code Composer Studio provides a memory browser that makes viewing and modifying the device memory a simple process. The window for Memory Browser contains many configurable options to choose which locations are read from and in what format. It can be opened by going to View and selecting the Memory Browser option.

The dropdown to the left of the address, allows you to choose whether data, program, I/O, or peripheral memory is being selected. The text box to the right of this is the address which is being read, which must be in hexadecimal with a preceding 0x. Once an address has been entered, a dropdown option for the data format of the memory appears. The data format displayed can be changed to various formats such as hex, integer, character, floating point, and so on.

On the top of the Memory Browser, are buttons that perform specific tasks. The first button lets you load, save, and fill memory each of which will open a separate window to choose the required options and data. The continuous refresh button, when selected, updates the contents of the location in memory at a constant rate configurable in the View menu option. The last button on the right is the Refresh button, which performs a single update of the contents of the view.

I hope you have found this introduction to embedded RAM helpful to your designs and implementations of TI's embedded processors and microcontrollers. For extended information, please see the link above.