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Hello, and welcome to the TI Precision Labs module, discussing power supply noise mitigation techniques. In a previous Precision Labs module, we discussed power supply noise, including the types and sources of power supply noise, how power supply noise rejection is measured and quantified, as well as how noise on each of the ADC power supplies impacts system performance. This module expands on those concepts by introducing several power supply noise mitigation techniques, beginning with PCB layout.

Layout optimization is by far the most important technique you can use to improve PSRR and maintain system performance. The component placement example shown here illustrates some important concepts that contribute to a PCB optimized for good PSRR. One specific layout optimization is to isolate switching noises by placing switching regulators away from sensitive analog inputs.

Switching regulators are great for their efficiency, but they can inject large transients onto supplies that couple into surrounding circuitry, including the ADC itself. If the power conditioning circuits are on the same side of the PCB as the signal chain components, the return current should never have to follow through the more sensitive analog circuitry. Additionally, always use proper supply decoupling.

There are two main classifications of decoupling capacitors-- bulk and local. Bulk decoupling capacitors are generally placed directly at the output of the supply source. These capacitors help filter the supply output and hold the voltage steady as the load current fluctuates. In addition, most active components will require at least one decoupling capacitor directly next to each of the main supply pins.

Local capacitors, such as the ones shown near the ADC analog supply pin, are generally much smaller in magnitude compared to bulk capacitors. Local capacitors are used to provide the instantaneous current demand from the device and filter out higher frequency noise. Some older ADC datasheets might recommend multiple capacitors in parallel as shown, where the smaller component is placed closer to the supply pins. However, this recommendation is related to older generation capacitors, where smaller value capacitors had lower Equivalent Series Inductance, or ESL, which provided a better high frequency response.

Modern ceramic capacitors typically have similar ESL for the same package size regardless of capacitance, so this requirement is no longer valid. Therefore, it is acceptable in most cases to just use one local decoupling capacitor, as shown here. Note that the 100 nanofarad capacitor is just an example in this case and that different components or supply pins can require more or less capacitance. Refer to the device datasheet for more information.

Routing is another important component to maintaining low power supply noise. For example, route power traces from the source to the pads of the capacitor and then to the device pins whenever possible. Placing a via to the plane between the pin and the capacitor pad is not recommended. Also, make the traces thicker for supplies that may carry higher amounts of current, for example, the analog and digital power supplies as shown.

Thicker traces help reduce the inductance between the bulk decoupling capacitors and the local decoupling capacitors. Finally, don't forget that ground is a supply, too. Ground serves as the current return path for both signals and supplies. Using a large ground port or plane with extra vias reduces the return path inductance and allows return currents to easily make their way back to the source.

Conversely, placing a ground port that extends for some length without sufficient connection to the ground plane can act as an antenna and will have a resonant frequency. This should always be avoided.

In a previous Precision Labs module that introduced power supply noise, we discussed how certain active components, such as clocks, can introduce large transients into a power supply. As an example, the image on the left shows a portion of the ADS127 L01EVM schematic that includes a decoupling component used by the ADC and clock fanout buffer. This buffer must be referenced to the same digital I/O level as the ADS127L01 digital supply DVDD, which may allow switching transients to couple on to the sensitive supply.

To maintain system performance, the EVM uses capacitors and a ferrite to decouple DVDD from the fanout buffer output supply, VDDO. The ferrite is highlighted in yellow in the image on the left. Comparatively, the ADS127/L01EVM layout image on the right shows a larger portion of the circuit and includes a schematic components from the image on the left within the gray box on the right. Note that the ferrite is highlighted in yellow, while the DVDD trace is highlighted in pink.

The next slide compares the power supply signal at the VDDO net, as well as the ADS127/L01 DVDD pin, as measured on the EVM. The image on the left, introduced on the previous slide, shows a portion of the ADS127/L01EVM including the clock circuitry and the ADC. Let's use the oscilloscope in the upper right to measure the power supply signals at VDDO and DVDD to understand how the ferrite helps reduce power supply noise.

First, let's measure VDDO at capacitor C63, which corresponds to the red oscilloscope lead. The plot in the upper right shows actual measured data from the EVM. With a light blue signal is the clock and the dark blue signal is VDDO. As shown, the clock signal couples to the VDDO supply, such that large transients are seen in this power supply voltage at both the rising and falling clock edges. This is exactly the type of response we want to avoid on sensitive ADC power supply input pins.

Comparatively, the response at the DVDD decoupling capacitor C73 corresponds to the green oscilloscope lead. Note how the transients measured at VDDO are effectively removed from the green oscilloscope capture on the bottom right, resulting in very little power supply noise reaching the ADC. Without the decoupling circuit shown in the schematic on the previous slide, the transients shown in the red plot would couple onto and DVDD affect the performance of the ADC.

However, proper decoupling ensures that these glitches are contained to the output of the clock fanout buffer. Another important power supply noise mitigation technique is frequency planning. This technique is critical when using switching power supplies where the switching frequency can couple onto sensitive supply traces. For example, the image on the left shows a generic block diagram for an adjustable DC/DC converter. The range of possible switching frequencies is given in the table on the bottom left.

In this case, implement frequency planning by choosing a switching frequency that is natively rejected by the rest of the system. As recommended in a previous Precision Labs module that introduced power supply noise, adding an LDO to the output of a switching converter can reduce coupling effects.

As an example, the image on the top right shows a PSRR versus frequency plot for Texas Instruments TPS7A48 LDO. Note that as the switching frequency increases, the PSRR of this LDO decreases. Therefore, choose the lowest acceptable switching frequency to benefit from the LDO PSRR as much as possible.

Alternatively, some ADCs include integrated LDOs that can be used for this purpose, as well. Refer to the ADC data sheet for more information. In either case, the ADC has frequency dependent PSRR specifications for each supply. The plot on the bottom right shows a PSRR versus frequency curve for the ADS127, a 24-bit wide bandwidth delta sigma ADC.

Note that the response is effectively flat at 110 dB for all supplies across frequency because this ADC has integrated LDOs on the supplies. However, there are some sensitivity on AVDD1 at approximately 400 kilohertz, which should be avoided when selecting a switching frequency. While we have only discussed adjustable frequency switching converters, frequency planning is still necessary for fixed frequency switching converters.

In this case, consider the PSRR response of the LDO and ADC and choose a component accordingly. Frequency planning can also be implemented by those ADCs that include a digital filter. The two most common types of integrated digital filters are the low latency filter shown on the top right and the wide bandwidth filter on the bottom right. On the left is the same adjustable frequency DC/DC converter shown on the previous slide.

ADC supplies will see a large boost in PSRR at frequencies that fall within the digital filter stopband. In delta sigma ADCs, the digital filter response repeats at multiples of the modulator frequency, F mod. Therefore, switching noise may alias into the ADC passband, if this noise happens to fall near the modulator frequency or any multiple thereof. If possible, choose a switching frequency that falls into one of the nulls of the filter to keep these signals from aliasing and improve the system PSR.

Since the ADC data rate is typically fixed by the system requirements, the frequencies highlighted by the red arrows are the recommended regions for switching frequencies based on the digital filter response. Conversely, if the data rate is flexible but the switching frequency is fixed, consider choosing the ADC output data rate such that it creates a null at the switching frequency. The next slide discusses several options for debugging power supply issues, including noise.

While developing a power supply for the ADC, verify several key parameters to rule out any potential issues and ensure a robust design. Start by reviewing key power supply specifications, such as the output current limits and the input/output voltage range of the component. Make sure to account for the total current consumption of all active components, sharing the supply and then budget for extra headroom.

Check the maximum capacitive load for the supply output, as all of the bulk and local decoupling capacitors on that supply are effectively in parallel and can add up quickly. Too much capacitance may produce slow start up times. Check that the LDO has at least the minimum dropout voltage between the input and the output and consider adding any other recommended noise reduction or feedforward capacitors for additional filtering. These are highlighted in yellow in the figure on the right.

If the power supply noise is still high, try increasing the size of ADC decoupling capacitors to provide additional filtering. This can be helpful not only on the main supply pins, but also on any internal voltage nodes brought out to a dedicated pin for external decoupling. The ADC manufacturer usually recommends capacitance values for these pins, as well.

To help identify the source of the noise, try replacing each of the ADC supplies with an external bench supply one at a time. If this does not reveal the issue, try replacing the main supply source for your board to determine where the noise is coming from. That concludes this video. Thank you for watching. Please try the quiz to check your understanding of this video's content.

Question one. Below are two layouts for a decoupling connection. Which is better? The correct answer is B, layout 2. This is because a decoupling capacitor is in parallel with the pin, as opposed to being connected with a stub as in layout 1.

Question two-- true or false. A ferrite should be added between the power supply of each device on the digital power bus. The correct answer is B, false. The ferrite was added to help decouple the ADC digital supply from the fanout buffer supply because the fanout buffer supply had clocking transients. This will not necessarily be the case for every device on the digital supply bus.

Question three-- choose the best answer. Thick traces are useful for power supply decoupling because they help-- The correct answer is A. Thick traces help reduce the inductance between bulk decoupling and local decoupling capacitors.

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