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Hello, and welcome to the TI Precision Labs module discussing clocking noise in precision ADCs. Although you may think of clocks as providing a digital input signal, these components can affect the analog performance of precision data acquisition systems. To further understand how clocks affect precision ADCs, this module discusses the topics of clock jitter, clock intermodulation, and clocking best practices for printed circuit board layout.

Under ideal circumstances, the clock provided to the ADC should have a constant sampling period. This is shown in the diagram at the top. Under these circumstances, the clock has no jitter.

However, a real clock signal has a measurable variation between sampling periods, such that every sampling period is slightly different. This is called clock jitter and is shown in the diagram on the bottom. Since all ADCs use a clock edge to control sampling point, clock edge variation results in deviations in the ADC sampling instance. This deviation results in the nonconstant sampling frequency that appears in the conversion result as another source of noise.

If you overlaid all of the individual sampling periods over a certain amount of time, they would look something like the combined sampling period shown on the right. This combined sampling period has a clock edge variation that is directly related to the amount of clock jitter.

Moreover, the clock edge variation is random and follows a Gaussian distribution, which is similar to most noise sources discussed so far in the Precision Labs series on noise.

If you were to sample an example sine wave input similar to the plot on the right, the sampling uncertainty error is also Gaussian, similar to thermal noise. Ultimately, the effect of clock jitter on ADC performance is primarily an increase in the ADC noise floor and, subsequently, the total thermal noise of the signal chain.

The amount by which the thermal noise increases depends on the input signal slew rate and the amount of clock jitter in the clock source. The equation at the bottom calculates the theoretical upper limit of the ADC signal-to-noise ratio, where f IN is the input signal frequency and t JITTER is the clock source jitter specification. For signals with higher frequency content, expect the signal slew rate to be higher and the SNR degradation from clock jitter to be worse.

As discussed on the previous slide, this equation calculates a theoretical upper limit of the ADC signal-to-noise ratio, where f IN is the input signal frequency and t JITTER is a clock source jitter specification.

The graph on the bottom left plots this equation to show the SNR across a range of input frequencies. Moreover, multiple clock jitter specifications are shown, ranging from 0.5 nanoseconds in red to 500 nanoseconds in dark gray.

All of these plots reiterate the previous claim that the noise increases and the SNR decreases as either the input frequency or jitter increase. The opposite is also true, however, such that the clock noise has virtually no impact on systems measuring DC or low-frequency inputs.

As a result, relatively noisy internal oscillators can be used in these applications and still maintain excellent performance. While these results are true in general, oversampling converters inherently help reduce the effects of jitter compared to Nyquist converters. This concept is explored in more detail on the next slide.

One key benefit to oversampling converters like delta-sigma ADCs is that the ideal SNR improves when using higher oversampling ratios, or OSRs. As an example, let's assume we are using a delta-sigma ADC to sample a sine wave similar to the one shown on the right.

Oversampling averages multiple samples over a defined period of time, which in turn averages out some of the sampling variation caused by clock jitter. This is also shown on the right.

As a result of this averaging, the overall SNR improves. The equation at the bottom quantifies the SNR improvement due to oversampling, which is simply an extension of the previous equation plus a term dependent on the delta-sigma ADC OSR.

Similar to the previous equation without the oversampling term, let's plot the equation at the top across a range of input frequencies and jitter specifications. This plot is shown on the left, where the OSR is selected to be 128.

Let's also include the previously derived plot for a Nyquist ADC that has no oversampling, which is shown on the right. One important difference between these two plots is that oversampling offers a 21 dB improvement in SNR compared to the equivalent jitter curves for the Nyquist ADC on the right. However, both plots illustrate the same effect.

As you increase the input signal frequency or amount of clock jitter, the resulting SNR decreases. Therefore, applications with higher SNR targets may require more expensive higher-power clocking solutions to minimize the jitter. Now that we have defined the SNR upper limit for both oversampling and Nyquist converters, let's examine how to set the clock jitter upper limit relative to other noise sources.

To understand how to set the SNR upper limit, assume we only have ADC noise and clock noise in the system. As a result, the total noise is given as the root sum of squares of both noise sources, as shown in the equation in the top right.

Next, assume that the clock noise is scaled by x, which is just some fraction of the ADC noise. This allows us to replace the clock noise term in the second equation on the right with a term equal to ADC noise divided by x. This can be further simplified as shown.

Finally, divide out the V N,ADC term such that the total noise is just the ADC noise multiplied by some scaling factor relative to x. Importantly, as x increases linearly, the scaling factor exponentially approaches 1. In other words, as long as the clock noise is a small fraction of the ADC noise, the total noise will be relatively unchanged. Let's apply some values to x and ultimately determine what the SNR upper limit should be.

The table on the bottom left shows some examples for x as well as a resulting scaling factor. The third column in the table shows how much the total noise increases as a result of the clock noise. For example, when x equals 3, which is when the clock noise is 1/3 of the ADC noise, the clicking noise causes a 5.4% increase in the total noise.

The last column translates this increase in noise into a relative SNR increase compared to the ADC SNR. For example, to ensure that there is only a 5.4% increase in the total noise compared to the ADC noise, ensure that the SNR upper limit is 9.542 dB greater than the ADC SNR. Further reduction in clocking noise requires larger SNR upper limit targets.

A common recommendation is to target a clock jitter specification that yields an SNR upper limit greater than or equal to 10 dB above the ADC SNR. Using this target ensures that the clock adds less than 5% additional noise to the system. The next slide uses an example to demonstrate how to translate this information to a jitter specification.

To begin this example, let's select an ADC and identify relevant parameters. The table shown in the center lists important data sheet parameters for the ADS127L11, which is a 24-bit, 1-MSPS, delta-sigma ADC designed for high performance, AC and DC measurements. Specifically, this table includes all available data rates for the wide-bandwidth filter and high-speed mode, as well as the corresponding OSR 3 dB frequency and SNR.

Importantly, these SNR values represent the performance of the ADC, which helps us set a limit on how much clock jitter can impact the overall system performance.

Specifically, the target SNR from clock jitter should be greater than or equal to 10 dB above the ADC SNR, as we determined on the previous slide. This helps ensure that noise due to clock jitter has little effect on the overall system noise. This is highlighted in the blue column in the table shown here.

Next, we can use the equation in the top right to calculate the allowable amount of clock jitter that ensures the target SNR is met. In this example, let's set f IN equal to the digital filter. 3 dB point to represent the maximum input signal frequency because this is where the effect of clock jitter is most apparent.

The calculated clock jitter values are shown in the red column in the table. One key takeaway from the results in the table is that increasing the OSR, which is equivalent to slowing down the ADC output data rate, improves the SNR performance. In general, systems that can support slower output data rates are measuring slower-moving input signals. These systems will experience less noise due to jitter, as the slight variations in the clock edges effectively go unnoticed by the ADC.

Comparatively, smaller oversampling rates and large input signal bandwidth requires much lower clock jitter. The values highlighted in yellow in the table indicate those settings where it is necessary to select a clock that has less than 50 picoseconds of jitter to avoid impacting the system SNR performance.

If a clock with higher jitter was selected for these settings, the noise from the clock jitter would actually limit the ADC's achievable SNR when using the full signal bandwidth. While not shown on this slide, one way to reduce the noise caused by clock jitter is by choosing an ADC that uses an integrated clock divider to produce the modulator sampling clock, such as the ADS127L11.

A clock divider acts on only one of the two input clock edges, typically the rising edge, to produce an output clock frequency that is no more than half of the original input clock frequency. Since it is reasonable to assume that some jitter exists on both input clock edges, dividing the clock in half effectively reduces the jitter on the output clock. Dividing down the input clock further continues to reduce the effect of the input clock jitter on the ADC. Next, let's analyze clock intermodulation.

Another way clock sources affect ADC noise performance and increase system noise is through clock intermodulation. Virtually all DAQ systems have multiple switching components that require a clock input. In some cases, these clock inputs may require different input frequencies that may be derived from separate clock sources.

The two green arrows represent examples of two different clocks-- CLK1 CLK2. These two clocks represent the frequencies f1 and f2, respectively. If these clock sources are discrete and asynchronous, they can potentially couple with each other and produce tones in the frequency spectrum.

Given the two clock sources at frequencies f1 and f2, the difference [? for ?] some of their fundamental frequencies produces intermodulation tones. These are called second-order intermodulation products and are represented by the red arrows.

Moreover, the clocks will have harmonics at multiples of f1 and f2. The clock harmonics are represented by the blue arrows. As a result, the sum or difference between the fundamental frequencies and other intermodulation products, including their harmonics, produce additional higher-order tones represented by the gray arrows.

While these tones may exist beyond the signal bandwidth of interest, they can still alias into the ADC passband and degrade AC specs, like SNR and total harmonic distortion. The next slide illustrates intermodulation effects in a real ADC.

Shown here is an FFT of data produced by the ADS127L01, a wide-bandwidth, 24-bit, delta-sigma ADC that is designed for high performance, AC and DC measurements. As the notes on the left show, the ADC inputs were shorted to mid-supply, such that the measured differential input voltage was 0 volts.

Additionally, the processor clock was set to 12 megahertz, while the ADC modulator clock was reduced to 11.996 megahertz, creating a difference of 4 kilohertz. Due to the difference in the processor and ADC clocks, a second-order intermodulation tone appears in the frequency spectrum at 4 kilohertz, with additional harmonics produced at multiples of 4 kilohertz. This illustrates how intermodulation products may fall directly into the passband of the ADC and contribute noise.

To mitigate this problem, wide-bandwidth applications often use one clock source to generate all other frequencies used in the system to ensure that they are all synchronous. If this is not possible, choose clock frequencies and sampling rates that are least likely to produce tones within the signal bandwidth of interest. Now let's consider clock signal integrity issues.

Under ideal conditions, we assume that the clock signals provided to the ADC look like the blue plot shown here. This clock has very consistent, monotonic rising and falling edges. Additionally, logic high and logic low are very clean, stable levels that should always be interpreted correctly by the ADC.

However, actual clock signals can have a variety of undesirable characteristics. An example of some of these behaviors are shown in the red plot.

Specifically, undershoot, overshoot, and ringing are identified in the actual clock signal plot on the right. These potential clock signal issues can cause the ADC to misinterpret the clock edges and cause undefined device behavior. Additionally, both undershoot and overshoot can violate the ADC absolute maximum ratings for the digital inputs.

As shown in the table in the top right, the ADS127L01 maximum voltage on the clock input pin is DVDD plus 0.3 volts. However, the overshoot in the red clock signal could extend well beyond these levels if logic high was 3.3 volts, for example. This violation of the ADC absolute maximum voltages can cause undefined device behavior or even long-term damage. Therefore, how can we mitigate this behavior?

To improve signal integrity, it helps to have a general understanding of why these issues occur. Shown in the top right is a generic transmission line circuit. This circuit consists of a driver that has some characteristic output impedance Z OUT, a 50-ohm trace, and a receiver that is assumed to have high input impedance.

In the context of signal chain design, the driver is part of the clock generation source, and the receiver is part of the ADC clock input circuitry.

When Z OUT does not equal the trace impedance, the clock signal reflects back to the driver at the location of the impedance mismatch. This can add to or subtract from the original signal, causing the overshoot, undershoot, and ringing shown in the red clock signal plot on the left. Though not shown, this can also result in a clock waveform that looks like it has shelves or steps in the edges.

To mitigate this issue, add a series resistance to the signal driver or source output. Typically, a resistance between 10 ohms and 50 ohms is sufficient. This resistance adds to the driver impedance to help match the 50-ohm trace impedance. A matched impedance dampens any clock reflections and minimizes the unwanted behavior in the clock signal plot on the left.

For more information, review the Precision Labs video that discusses "PCB trace impedance matching." The next slide discusses some best practices for routing and laying out clock circuitry on a PCB.

When designing the PCB layout for your clock source, take care to keep the clock signal as clean as possible. Although it is considered a digital input, treat the clock signal as if it were another important analog signal. As an example, a portion of the ADS127L01 EVM layout is shown here. Note that only the circuitry related to clocking, as well as the ADC, have been included to avoid confusion.

The ADS127L01 shown on the bottom right was introduced on a previous slide discussing intermodulation distortion. This wide-bandwidth, delta-sigma ADC requires a high-speed, low-jitter clock, which is shown in the upper left.

The clock output, highlighted in red, is fed into a clock fanout buffer. This is component U23 in the upper left. The clock fanout buffer generates two identical copies of the original input clock frequency. The first is provided to the controller through resistor R55.

The second signal continues on towards the ADC through R56, a small 43-ohm resistor in series with the clock buffer output. This resistor helps match the trace impedance and dampen reflections as discussed on the previous slide. The buffer keeps the ADC and controller clock synchronized.

The ADC clock signal then passes into two D flip-flops, which are U24 and U25. These components divide down the clock buffer output to produce the clock for the two modes, which are low power mode and very low power mode.

These divided-down signals, along with the original clock signal, then pass through a jumper to select which one is supplied to the ADC. Importantly, all three mode choices are synchronous to the original clock source. In this example, the solid red line passes through the high-resolution mode selection jumper.

After the jumper, the selected clock signal passes through another resistor, R60, and a shunt capacitor, C76, before reaching the ADC clock pin. These components act as a filter to help slow down the clock edges in case of additional overshoot. Note that this path is kept as short and as direct as possible.

Another option to improve clocking circuitry performance and reduce clocking [? transience ?] from coupling into the ADC output is to place a small ferrite bead between the ADC digital supply pin and the clock source or buffer supply pins. This topic is discussed in more detail in the Precision Labs presentations that introduce power supply noise in ADC systems.

Finally, it is always best practice to route clock traces away from digital communication and other noisy circuitry.

That concludes this video. Thank you for watching. Please try the quiz to check your understanding of this video's content.

Question 1-- which ADC requires a lower clock jitter specification? The correct answer is B, an 18-bit SAR converter optimized for a 1 MSPS sampling rate.

Question 2-- assume a 24-bit delta-sigma converter operating at 400 kSPS is being used to measure 1-kilohertz and 100-kilohertz signals. Which of the following is true?

The correct answer is B. The jitter noise is related to both the signal frequency and the clock jitter. Therefore, the 100-kilohertz signal has the highest jitter noise.

Question 3-- which of the following statements are false? The correct answer is B. A clock termination resistor minimizes power dissipation in the driving gate.

Question 4-- when examining the FFT of data collected from an ADC, an unexpected signal is detected. What could be the cause of that signal? The correct answer is C, intermodulation of the communication and ADC clocks.

This video is part of a series