Choosing the best ADC architecture

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Hello. My name is Luis Chioye. I am an applications engineer with Texas Instruments Precision Data Converter Team.

And I'm Anthony Vaughan, with TI's Precision Analog Marketing Team. Today we're going to give you an overview of some of the most popular analog-to-digital converter architectures in use today, and highlight the advantages of each when used in different applications.

When selecting an analog-to-digital converter, or ADC, for a particular application, the first step is to understand the advantages of each topology, and choose the best architecture to fit the application needs.

This table shows three of the most common ADC architectures offered by Texas Instruments, SAR, Delta-Sigma, and Pipeline. Each of these architectures offers distinct performance advantages.

The success of approximation register converter, or SAR ADC, is often considered the backbone of general purpose mixed signal circuits. TI's Precision SAR ADC portfolio ranges from 8 to 18 bits of resolution, and up to about 4 mega samples per second of throughput. SAR converters achieve moderate speeds at medium-to-high resolutions, with a high level of DC and AC accuracy. Therefore, SAR ADCs are used in many data acquisition applications, including control loops, power monitoring, and low-to-medium frequency analysis.

Other advantages of SAR converters include negligible or zero latency, and ultra-low power consumption. The power consumption of most SAR ADCs is directly proportional to the sampling rate. When configured at low sampling rates, some of these devices will consume power measured in the nanowatts. This makes them suitable for use in coin cell battery powered applications, where low power is of the utmost concern. Many SAR ADCs are also available in very small packages, making them perfect for use in space-constrained designs.

Delta-Sigma converters offer the highest resolution versus the other ADC architectures. These devices are capable of producing 16 to over 24 bits of resolution. The Delta-Sigma offers high-resolution performance, while providing high stability. They have moderate power consumption and provide a high degree of integration, often replacing several components in a data [INAUDIBLE] system.

All Delta-Sigma ADCs incorporate additional filters, typically optimized for an application requirement. And this advantage compared to the other architectures is in some cases cycle latency.

Pipeline converters are very high-speed devices, offering data rates exceeding 10 mega-samples per second with resolutions ranging 12 to 16 bits. Pipeline converters are many times found in wireless space stations, and in high-speed instrumentation, and high-speed spectrum analysis applications. While broad generalizations can be made about these ADC architectures, overlap in performance and exceptions do apply.

We will now focus in on the SAR and Delta-Sigma converter architectures.

A key difference between the SAR and Delta-Sigma topology is in how the sampling of the input signals relate to the data conversion result. The SAR converter takes a sample or a snapshot of the input, and captures the signal level at a specific point in time, and performs a conversion. Therefore, SAR ADCs can provide very low latency results, and may be used in applications with both continuous and discontinuous signals.

The Delta-Sigma continuously samples a signal for a period of time, and outputs conversion data that corresponds to the average of samples over a period of time. It is important to remember the way Delta-Sigma converters operate, particularly for the science incorporating multiplexing and synchronization. Delta-Sigma converters provide best results when used to convert continuous signals.

The SAR converter only samples a signal once for each conversion. The sampling on the SAR ADC is controlled by a start conversion signal. Therefore, SAR ADCs allow a very precise control of the point in time where the sampling occurs. This feature can be an advantage in applications that require synchronization of the sampling to an external event, or applications that require a fast transient capture.

Particularly in control applications where measurements may need to be synchronized to the application of an external stimulus, the SAR topology is the most flexible, and will likely provide the lowest latency from that event. Thus, SARs are often considered a better choice for control systems, where the loop time must remain highly predictable and as short as possible.

The Delta-Sigma converter averages multiple samples for each conversion result. The Delta-Sigma continuously samples the signal for a period of time, and outputs conversion results corresponding to the average of samples over a period of time. The averaging performed by the converter occurs in the form of additional filter.

It is important to remember the way Delta-Sigma converters operate, particularly for the science incorporating multiplexing and synchronization. It is easy to synchronize Delta-Sigma converters together. So they start sampling at the same time. But it may be challenging to precisely synchronize the sampling of the Delta-Sigma converter to an external event.

While they can also be used in control loops, these are usually more difficult applications. Because it is difficult to determine exactly what data output correlates to which sampling instance. Therefore, Delta-Sigma converters are most often used in applications that require converting continuous signals with a high level of resolution.

We will now go into a little more detail on how a SAR ADC works. The conversion process in a SAR ADC works in a similar fashion to a weight balance. The conversion process in a SAR ADC is performed in two steps, a sampling or acquisition phase, and a conversion phase.

During the sampling phase, the input signal is captured in the sample and hold capacitor. The conversion begins immediately after the sampling phase. During the conversion, the sample and hold capacitor is disconnected from the external input circuit, and is converted into a digital code proportional to the input voltage. The SAR ADC incorporates an internal capacitor array with binary weighted values.

Each capacitor holds a binary weighted value of the reference voltage. The input sample voltage is compared with the voltage of the most significant bit or MSB, and a decision is made for the most significant bit. The same test is repeated for each following bit. And a decision is made for its binary weighted value. Each binary weighted bit value is compared to the sample voltage, until the least significant bit has been tested, and the final conversion result is obtained at the end of conversion.

For more information about precision ADCs, or to order a development kit, visit the TI Precision ADC web page at ti.com/precisionadc. We hope that you have found this overview useful. Thank you for watching.

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