Engineer it - Linear & low drop-out regulators (LDOs)

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Hi there. I'm David Hopkins. I'm here from TI's LDO and Supervisor product line, and today I'm going to talk a little bit about LDO stability and how to stabilize your LDO control loop. But first, let's go a little bit into classical LDO control theory so you have an idea of what I'm talking about.

So if we look here, with a normal LDO you have a very traditional control loop. You have your pass element, which is represented here by your plant, your feedback network, which is going to be your feedback part of the control system, and then you have the summing amplifier, well the different amplifier that is called the error amplifier for an LDO. In an ideal world, this is how an LDO would work.

In a less ideal world, we go to this for a model of the LDOs and their control loop and we factor it within quite a bit more in the plant. First we factor in the error amplifier as part of the plant and the frequency response of the error amplifier, and then we also factor in the load.

The load can be also shown independent of this, but then you have to change the plant transfer function. So to loop those two together, I threw the load into the plant transfer function. And again, your feedback network represents just the feedback resistors. And the summing difference here includes the error amplifier in an ideal setting and the plant's now encapsulating the error amplifier's frequency response.

So with a traditional LDO, we can look at these equations and how they're normally compensated. These equations give you a rough idea. If you want more details on how to do pole zero compensation for an LDO, there are several app notes online. The one listed below I think is quite good.

But now let's move on a little bit and talk about some of the other nuances that a lot of the app notes and a lot of material online for LDO stability don't talk about. So the first one we're going to look at is a parasitic. We're going to look at three different parasitics. The first parasitic is capacitor replacement.

In an ideal world, you want your capacitors as close as possible to the pins through your LDO, if not on top of the pins. The reason for this is, as you can see in this small signal model, is you add any parasitic resistance and inductance between your capacitor and your plant transfer function, which is the error amplifier, and the pass device, which is represented here by the dependent current source to show off what a MOSFET will do in saturation. This is a PMOS architecture.

And then here you have your feedback network. And ideally for a real LDO what you want to do is you want to have your output node here and your input to be an AC Ground, to be as close as possible to 0 volts AC. And the more parasitics you add in because you push your input and output capacitors further away, then it gets a lot harder for the LDO to actually be stable. So just place them very close.

The next parasitic that we're going to look at is the capacitor type. Different types of capacitors such as aluminum electrolytic, ceramic, and tantalum capacitors have different properties. For example, aluminum electrolytic-- very high capacitance values, but they have a very high ESR.

Now this high ESR can cause a lot of issues with various LDOs, and depending on the LDO data sheet, really a lot of this comes down to just read the LDO data sheet and it will tell you what capacitor types it's compatible with because it's internal compensation will be set up in such a way to cover the various types of capacitors.

And the reason for this is if, again, we're going to go back to the small signal model. If you look, the ESR and ESL here and here on the input and output capacitors will cause a lot of problems with the plant controller function because when you add them in, you ideally, again, Vin and Vout to be an AC ground. And for that to happen, especially at high frequency, the input capacitance here has to be a short to ground and the output capacitance has to be a short to ground.

And you need the input impedance to be as low as possible. And you ideally want your output impedance low, so that way you have as good of a connection to ground as you can for AC analysis. This helps ensure that your control loop is stable.

And when you do not have this, such as when you have an aluminum electrolytic output capacitor here, the aluminum electrolytic will have a high ESR and high ESL. These two factors combined will cause it to basically dip in frequency very quickly and it loses its effectiveness in the tens to hundreds of low hundreds of kilohertz region. And because of this, it turns inductive. All these mechanisms will make the control loop of the LDO unstable because it is no longer capacitor at high frequency in the AC model, it is a inductor now.

So going on from capacitor types, as I said, the capacitor types are all explained in the data sheet, so the various LDOs. Want to look at LDO loading and how the LDO load affects the stability of the LDOs control loop.

Now, if you look on a small signal model, that pass element-- this being a P-FET. It's governed by its small signal model, which is GM times VGS. It's trans conductance versus the gate to source voltage. And for this being a P-FET for easy use, I flipped the source and the gate voltage to always keep it positive. So the source voltage I have here, and the gate voltage is the output of the error amplifier. This times the inherent transconductance of the pass element gives it the current that's being pumped through it, and which gives a lot to the output impedance of the LDO. And the output impedance of the LDO directly affects its stability. And, however, at the same time you have to remember that the current going through an LDO is going to be equal to the current going out of an LDO. And so you see here I have V-out over the load impedance, because that will directly control how much current is going through this current source.

So depending on the amount of current going through an LDO, this is actually where a lot of older LDOs have issues. When they are at low current or no load whatsoever, they go unstable because the [? VSG ?] here wants to go to zero as quickly as possible. And it really doesn't know what to do not driving any load current, therefore creating an unstable control loop. Now to illustrate some of these effects, we can go here to the bench where I've set up a load transient FET

This is our load transient power FET and the board around it. The power FET is one TI's next FETs that is specialized for high frequency and high power switching, and serves our purpose very well as a load transient FET. And what this FET will allow me to do is that using this function generator here, I can quickly drive the gate of the past FET, and I have a resistor in series from the drain of it to ground. And it'll let me quickly switch in a high load resistance, and cause a big load transient with very-- yeah, very quickly. And then I go over to the unit I will be testing, which is a TPS 7-8300.

It is a two amp LDO that's capable of around 4 to 6 microvolts RMS noise. And it has a very fast transient response. But at the same time, it has some unusual capacitor requirements in that its minimum output capacitance is 22 micro ferret. And its minimum input capacitance is 10 micro ferret, which is-- can be considered quite a bit for an LDO like this, but a lot of that goes down to how high its PSR is. And how low noise it is. It is a very high performance LDO.

Here's the VM we're using. It is the TPS 7-8300. The LDO is here. And I've modified the CVM by removing the output capacitors-- that should be right here-- and replacing them instead with the 22 micro ferret aluminum electrolytic output capacitor here. And the idea of this experiment is that when I hit the trigger button on the function generator, I'm going to drive the gate at this power FET, which will in turn switch in a one ohm resistor in series with the LDO's output to ground.

This will cause 0 to 2 amp load transient. And if the LDO is stable, it should recover nicely from the load transient and keep regulation. If it is not stable, you will see quite a number of oscillations. So now we go over to the oscilloscope. And as you can see here-- well actually, let me retrigger this for you. So, the first channel in yellow is the input voltage. The second channel in pink is the output voltage. Both of these channels are AC coupled to really show off the load transient and what it does. And the third channel in green is the output current from the LDO. And how quickly it steps up and down. At the start of the load current, you see both the input take a big dip and the output voltage take a big dip.

The reason for both of them having a dip is that you're going from 0 to 2 amps that you're pulling out of it. So you're going to discharge any of the capacitors on the board trying to supply that current. Now if we go on, take a closer look at the input voltage. You see that the input voltage seems to be ringing-- especially here in the center where it should be stable. This seems a little bit odd, but if you look closer at the output voltage you notice a lot of this ripple almost that's happening. It's not ripple. It is actually the LDO oscillating due to the aluminum electrolytic output capacitance.

And if we zoom in on this, you can get a little bit better of an idea. Let me retrigger so we get a clearer picture of it. You can see where it dips down initially due to the load transient. Comes back up. And as soon as it comes back up, it's oscillating. Now as a linear regulator, it really shouldn't be oscillating. And this signifies an unstable control loop. A load transience is a really good, quick method to check for stability because when you do a zero to full-load load transient, you'll see this. Now we're going to pause for a little bit while I change out this EVM for a EVM that has not been modified with the 3 10 micro ferret ceramic output capacitors. And we're going to show a repeat of this experiment with a stable LDO.

I have now replaced the EVM with a stock TPS 7-8300 EVM. This EVM comes with 3 10 micro ferret output capacitors, which is an ideal output capacitance for this part. The reason for using 3 10 microphone output capacitors in parallel is, it gives you a lower ESR and ESL to the output capacitors, giving you a higher quality output capacitance. And it also gives you a smaller footprint. And you'll see this actually helps quite a bit with the load transients. And actually let's repeat that experiment that we did earlier where we found that it would oscillate with aluminum electrolytic output capacitor.

So I'm gonna go back. Same exact set up as before. And just simply retrigger the function generator. And as you can see, on the wave forms, you have your input supply. It is AC coupled. The second channel in pink is your output voltage. This is also AC coupled. And the third channel in green is the output load current. This is your 0 to 2 amp pulse. Then you can move up. And what you can see in the actual response though is, on the input voltage you see this ringing here as soon as you get that load step. And you also see the ringing on the far side. What this ringing means is that it's an under damped control loop, which Is typically done for fast transient response on power supplies. But the overvoltage runs the risk of damaging sensitive electronics, such as A6 and FPGs.

Now going to the output of the TPS 7-8300 with the ceramic output caps, I see it as a perfect, critically damped-- maybe a little bit overdamped response-- where you drop as you pull current out of the output capacitance. And you come back on a nice recovery back into normal regulation to the output voltage. And as you release the two amp load pulse, you go back up because the LDO is still sourcing two amps but the load isn't there anymore. And the LDO catches up in time. And the remaining charge on the capacitor's discharge the other passage, which is a feedback network. And you return to normal LDO regulation. Thank you for watching. And for more information, please see the following links.