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Precision labs series: I2C
TI Precision Labs (TIPL) is the most comprehensive online classroom for analog signal chain designers. The interface series provides technical training for commonly used protocols across industrial, automotive and many more applications. Start the I2C series to learn about the I2C standard, the basics of the data protocol and the physical signaling used, and how translator and buffer devices can be used to resolve application-level issues.
I2C hardware overview
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Hello, and welcome to Precision Labs training of the I squared C hardware overview. In this video, we'll discuss how the protocol is implemented in hardware at its most basic level. And we will discuss some of the key design parameters for implementing I squared C hardware.
The inter IC, or I squared C interface was created in 1982 to address the need for a simple, robust, low cost protocol for communicating between ICs while using the least amount of pins. As a variety of peripheral parts increased and the benefits of the I squared C interface became obvious to system designers, the I squared C interface rapidly increased in popularity, and was widely adopted shortly after it was released as a standard.
There are an enormous range of devices that use the I squared C interface. And system designs are only limited by their own creativity. Here are just a few types of devices that can be used-- IO expanders, temp sensors, light sensors, memory, keypad scanners, pressure sensors, humidity sensors, ADCs, DACs, and a variety of other devices used in the I squared C protocol.
The I squared C bus is a very popular and powerful bus used for communications between a master or multiple masters and a single or multiple slave devices. The bus is composed of only two wires, SDA, which is a serial data line, and SCL, which is a serial clock line. Both SCL and SDA have an open drain or open collector drive with an input buffer that supports bi-directional communications or data transfer.
As we see here, the master pulls down the bus and is thus generating the low signal on the bus. We then see the slave pull the bus down and then generate the low signal. Thus, it is bi-directional in nature. We will cover more hardware aspects later in this video.
The I squared C protocol is an eight-bit data structure, which is a common data format for most microcontrollers and processors. That allows for the masters to communicate with slaves with either a seven-bit or potentially 10-bit addresses.
Of the eight bits, seven of the bits are for the address. And the last bit is for indicating the direction of the message, where a high indicates a read and a low indicates a write operation. The I squared C protocol is address based, meaning that all slaves must have a unique address. This address is done in hardware, usually by connecting address pins to either a logic high or low.
In this example, we see the address pin A2, A1, A0 pull to ground. Thus, the address in binary is 1, 1, 1, 0, 0, 0, 0, which is 70 in hex. Some slaves don't have address pins, and they have a static internal address that cannot be changed.
Having a bus composed of parallel connections is unique and advantageous because adding devices is as simple as connecting to the bus at any location. Furthermore, those editions of slaves can be done at any time. The I squared C bus has various operating modes. Each mode covers a range of operating clock frequencies and has a variety of limits that bound the protocol.
The most important requirement for each mode is a max clock frequency, max bus capacitance, and max rise time, which are all defined in the I squared C standard. The three most common modes of operation are standard mode, which operates between 0 and 100 kilohertz, has a max bus capacitance of 400 picofarads, and has a max rise time of 1,000 nanoseconds.
Fast mode, which operates between 0 and 400 kilohertz, has a max bus capacitance of 400 picofarads, and has a max rise time of 300 nanoseconds. And fast mode plus, which operates between 0 and 1,000 kilohertz, has a max bus capacitance of 550 picofarad, and has a max rise time of 120 nanoseconds.
Let's reiterate. The I squared C protocol physical layer is a simple two-wire bus that uses an open drain architecture to achieve bi-directional communications, as opposed to other interfaces that use push/pull or differential drivers. Masters and the slaves have an input buffer for both SCL and SDA, and can have an open drain driver for both SCL and SDA.
There will always be an external circuit to generate the high. And in most cases, this is performed by the pull-up resistor. This indicates that either the slave or the master can generate a zero or low by pulling down on the bus with an open drain driver. In other words, turn on an N channel that are in some cases bipolar NPM. The high is completely dependent on the pull-up resistors.
It's important to note that the I squared C standard specifies the max total bus capacitance for each mode of operation. This includes the parasitic capacitances on the bus due to the traces which are a function of width, length, dielectric material, and the distance between the bus and its return path ground. Each device in the bus also adds additional capacitance to the bus.
The total amount of the bus capacitance C bus is limited in the I squared C standard for each mode of operation, which defines the max clock frequency. In order to meet the timing requirements for the mode of operation used, we need to be within the max rise time specification. The max rise time specification for SCL and SDA is controlled by the RC time constant created by our pull-up NC bus, and is defined as the amount of time it takes to transition from VIL to VIH.
This concludes this video. Thank you for watching. Please try the quiz to check your understanding of this video's content.