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TI’s new wideband digital pre-distortion processor achieves power amplifier efficiencies of up to 40 percent for wireless communications applications

Highly integrated transmit solution delivers more than 20 MHz of signal bandwidth

Bangalore , Feb. 12, 2009 - In an effort to drive the proliferation of green technology in communications infrastructure, Texas Instruments (TI) (NYSE: TXN) today introduced a new single-chip wideband digital pre-distortion transmit processor that enables OEMs to improve power efficiency and ultimately reduce the overall power consumed by wireless basestations. TI’s high-performance GC5325 combines a crest factor reduction block (CFR) and a digital pre-distortion block (DPD) to improve power amplifier (PA) efficiencies to more than 25 percent for Class AB PAs and more than 40 percent for Doherty PAs. The flexible GC5325 supports multiple PA architectures, multi-mode operation, and various air interface standards including: CDMA2000, WCDMA, TD-SCDMA, OFDMA (WiMAX, LTE), HSPA, and HSPA+.

“OEMs are aggressively looking for new ways to meet wireless service providers' green initiatives. Digital pre-distortion combined with crest factor reduction is a way to make a significant impact on lowering overall power consumption in basestations, remote radio heads, and wireless digital repeaters.,” said Apoorva Awasthy, Business Development Manager, Texas Instruments India.

“Our customers can use the GC5325SEK, in conjunction with their own Power Amplifier, and within an hour, be able to demonstrate the real-world advantages of TI’s crest factor reduction block / digital pre-distortion block solution. We have a GC5325SEK set up in Texas Instruments Bangalore which can demonstrate the performance of this device on WIMAX and MC GSM applications”, Mr Awasthy added.

The GC5325 DPD transmit architecture incorporates a TI floating point digital signal processor (DSP) to implement the advanced linearization algorithm which relaxes multi-carrier power amplifier specifications and increases PA operating efficiencies. The GC5325 device has greater than 100 MHz of DPD bandwidth which allows for correction of over 20 MHz of 5th order distortion products.

System level performance can be evaluated in the manufacturer’s design with the easy-to-use GC5325 system evaluation kit (GC5325SEK). Engineers can measure PA efficiency, Error Vector Magnitude (EVM), Peak-to-Average Ratio (PAR), and Adjacent Channel Leakage Ratio (ACLR). In addition, customers can save four man months of development time by leveraging the GC5325SEK architecture to implement their own design. The GC5325SEK consists of a dual-transmitter architecture, supporting transmit diversity, multiple-input and multiple-output (MIMO), and beamforming for smart antenna applications. The GC5325 uses a composite baseband input consisting of single or multiple carriers combined into a single digital signal, allowing customers to leverage their existing Digital Up-conversion (DUC) IP as well as TI’s complete signal chain solutions for communications infrastructure applications. The GC5325SEK utilizes TI’s TMS320C6727 low-cost, floating-point DSP in addition to the DAC5682z (1GHz dual interpolating DAC), ADS6149 (Low power 14-bit, 250 MSPS ADC), and TRF3703 (400 MHz – 4 GHz IQ Modulator).

GC5325 features and benefits

  • High integration reduces design complexity, power consumption, development time, board space, and bill-of-material costs.
  • CFR processing block reduces the peak-to-average ratio (PAR) for multi-channel/multi-carrier signals.
  • Fully adaptive linearization reduces adjacent channel leakage ratio (ACLR) by 20 dB or more.
  • Improves efficiencies to more than 25 percent for Class AB PAs and more than 40 percent for Doherty PAs.
  • Two GC5325 devices can be used to implement a dual-transmitter architecture with a single DSP and shared feedback path, thereby reducing the bill of materials for diversity or MIMO applications.
  • Flexible DSP linearization algorithm supports existing and emerging wireless standards.
  • Complete signal chain and system evaluation kit reduces time-to-market and design risks.

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