Texas Instruments 1.25-GSPS, 16-bit DAC slashes power consumption 65 percent, increases speed 25 percent
Combines best-in-class energy efficiency, speed and size for 3G, LTE, WiMAX base stations and repeaters, and software defined radios
Bangalore (March 22, 2011) – Texas Instruments Incorporated (TI) today introduced the industry’s most power-efficient 4-channel, 16-bit DAC (digital-to-analog converter). At 1.25 GSPS, the DAC3484 is 25 percent faster than the next fastest quad DAC while consuming as little as 250 mW per channel – 65 percent less than the closest competitor. The DAC3484 is also 40 percent smaller than alternative quad DAC solutions while enabling wideband power amplifier linearization of up to 250 MHz. The wider input bus DAC34H84 or the 2-channel DAC3482 are available to support a linearization bandwidth up to 500 MHz. For more information and to order samples, visit www.ti.com/dac3484-pr.
“With the green movement assuming a compelling importance across industries, wireless base station manufacturers face the challenge of delivering systems which are low power, high performing and can support wider bandwidth”, said Apoorva Awasthy, Business Development Manager, HPA, TI India. “DAC3484 helps solve power consumption and miniaturization challenges in 3G, LTE and WiMAX base stations, wideband repeaters and software defined radios”, Mr. Awasthy added.
“Wireless base station manufacturers are challenged to deliver systems that push the limits of bandwidth and performance while keeping power consumption in check,” said Steve Anderson, senior vice president of TI’s High Performance Analog business. “The DAC3484 and its two related DACs can help customers designing 3G, LTE and WiMAX base stations, wideband repeaters and software defined radios optimize their systems for energy efficiency in a smaller footprint.”
Key features and benefits
- 16-bit interleaved 1.25-GSPS input halves the I/O count, reducing FPGA costs and simplifying board routing.
- 9-mm x 9-mm Multi-row QFN package enables higher-density main and diversity transmitters.
- Low-jitter 2x to 32x phase locked loop eliminates the need for an external, low-jitter clock multiplier to match the interpolated rate.
- 2x to 16x interpolation and two independent 32-bit NCOs (numerically controlled oscillators) lower the interface rate and cost of FPGAs, while providing flexibility in frequency planning.
- Offset, gain, group delay and phase control for system calibration significantly improve sideband suppression for wideband signals when interfacing with IQ modulators, such as the TRF372017, in direct up-conversion radios.
Tools and support
Evaluation modules (EVMs) are available. The DAC3484EVM, DAC3482EVM and DAC34H84EVM include the TRF370315 IQ modulator and CDCE62005 clock jitter cleaner, as well as TI power management devices, such as DC/DC converters and low-noise LDOs, to provide a complete bits-to-RF prototyping and reference design. The EVMs are also compatible with the GC5330SEK, a complete transmit, receive and digital pre-distortion system evaluation kit and reference design for power amplifier linearization.
Additionally, the TSW3100 pattern generation module features a high-speed double data rate LVDS (low-voltage differential signaling) data output bus that provides 16 bits of data at 1.25 GSPS per bit. When combined with the DAC3484EVM, the TSW3100 enables easy data pattern generation while offering a flexible evaluation environment.
An IBIS model to verify board signal integrity requirements is also available.
Learn more about TI’s data converter portfolio by visiting the links below:
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